LAN9353 Datasheet, PDF (346/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
12.3 I²C Master EEPROM Controller
The I²C EEPROM controller supports I²C compatible EEPROMs.
Note: When the EEPROM Loader is running, it has exclusive use of the I²C EEPROM controller. Refer to Section
12.4, "EEPROM Loader" for more information.
The I²C master implements a low level serial interface (start and stop condition generation, data bit transmission and
reception, acknowledge generation and reception) for connection to I²C EEPROMs and consists of a data wire (EESDA)
and a serial clock (EESCL). The serial clock is driven by the master, while the data wire is bi-directional. Both signals
are open-drain and require external pull-up resistors.
The I²C master interface runs at the standard-mode rate of 100 kHz. I²C master interface timing information is detailed
in Figure 12-2 and Table 12-1.
FIGURE 12-2:
I²C MASTER TIMING
EESDA
(in)
EESDA
(out)
S
EESCL
t_hd;dat;in
t_sp
t_{su;dat;in tsu;dat;out}
t_low
t_f
t_hd;sta
t_high
t_r
Sr
t_su;sta t_sp
t_sp
TABLE 12-1: I²C MASTER TIMING VALUES
Symbol
f_scl
t_high
t_low
t_r
t_f
t_su;sta
t_hd;sta
t_su;dat;in
t_hd;dat;in
t_su;dat;out
Description
EESCL clock frequency
EESCL high time
EESCL low time
Rise time of EESDA and EESCL
Fall time of EESDA and EESCL
Setup time (provided to slave) of EESCL high
before EESDA output falling for repeated start con-
dition
Hold time (provided to slave) of EESCL after
EESDA output falling for start or repeated start con-
dition
Setup time (from slave) EESDA input before
EESCL rising
Hold time (from slave) of EESDA input after EESCL
falling
Setup time (provided to slave) EESDA output
before EESCL rising
Min
4.0
4.7
5.2
Note 1
4.5
Note 1
200
Note 2
0
1250
Note 3
t_hd;dat;out
Typ
t_buf
P
S
t_su;sto
Max
100
1000
300
Units
kHz
s
s
ns
ns
s
s
ns
ns
ns
DS00001925A-page 346
 2015 Microchip Technology Inc.