LAN9353 Datasheet, PDF (304/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.7.3.17 Switch Engine Global Ingress Configuration Register (SWE_GLOBAL_INGRSS_CFG)
Register #:
1840h
This register is used to configure the global ingress rules.
Size:
32 bits
Bits
Description
31:18
17
16
15
14
13
RESERVED
Enable Other MLD Next Headers
When set, Next Header values of 43, 44, 50, 51 and 60 are also used when
monitoring MLD packets.
Enable Any MLD Hop-by-Hop Next Header
When set, the Next Header value in the IPv6 Hop-by-Hop Options header is
ignore when monitoring MLD packets.
802.1Q VLAN Disable
When set, the VID from the VLAN tag is ignored and the per port default VID
(PVID) is used for purposes of VLAN rules. This does not affect the packet
tag on egress.
Use Tag
When set, the priority from the VLAN tag is enabled as a transmit priority
queue choice.
Allow Monitor Echo
When set, monitoring packets are allowed to be echoed back to the source
port. When cleared, monitoring packets, like other packets, are never sent
back to the source port.
12:10
9
8
7
6
5
This bit is useful when the monitor port wishes to receive its own MLD/IGMP
packets.
MLD/IGMP Monitor Port
This field is the port bit map where IPv6 MLD packets and IPv4 IGMP pack-
ets are sent.
Use IP
When set, the IPv4 TOS or IPv6 SC field is enabled as a transmit priority
queue choice.
Enable MLD Monitoring
When set, IPv6 Multicast Listening Discovery packets are monitored and
sent to the MLD/IGMP monitoring port.
Enable IGMP Monitoring
When set, IPv4 IGMP packets are monitored and sent to the MLD/IGMP
monitor port.
SWE Counter Test
When this bit is set the Switch Engine counters that normally clear to 0 when
read will be set to 7FFF_FFFCh when read.
DA Highest Priority
When this bit is set and the priority enable bit in the ALR table for the destina-
tion MAC address is set, the transmit priority queue that is selected is taken
from the ALR Priority bits (see the Switch Engine ALR Read Data 1 Register
(SWE_ALR_RD_DAT_1)).
Type
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
-
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
DS00001925A-page 304
 2015 Microchip Technology Inc.