LAN9353 Datasheet, PDF (45/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 5-1:
Address
170h
174h
174h
178h
178h
178h
17Ch
17Ch
17Ch
180h
180h
184h
188h
18Ch
1A0h
1A4h
1A8h
1ACh
1B0h
1B4h
1B8h
1BCh
1C0h
1C4h
1C8h
1CCh
1D0h
1D4h
1D8h
1DCh
1E0h
1E4h
1E8h
1F0h
1F4h
1F8h
SYSTEM CONTROL AND STATUS REGISTERS (CONTINUED)
Register Name (Symbol)
1588 GPIO x Rising Edge Clock NanoSeconds Capture Register (1588_GPIO_RE_CLOCK_NS_-
CAP_x)
1588 Port x RX Message Header Register (1588_RX_MSG_HEADER_x)
1588 Port x TX Message Header Register (1588_TX_MSG_HEADER_x)
1588 Port x RX Pdelay_Req Ingress Time Seconds Register (1588_RX_PDREQ_SEC_x)
1588 Port x TX Delay_Req Egress Time Seconds Register (1588_TX_DREQ_SEC_x)
1588 GPIO x Falling Edge Clock Seconds Capture Register (1588_GPIO_FE_CLOCK_SEC_CAP_x)
1588 Port x RX Pdelay_Req Ingress Time NanoSeconds Register (1588_RX_PDREQ_NS_x)
1588 Port x TX Delay_Req Egress Time NanoSeconds Register (1588_TX_DREQ_NS_x)
1588 GPIO x Falling Edge Clock NanoSeconds Capture Register (1588_GPIO_FE_CLOCK_NS_-
CAP_x)
1588 Port x RX Pdelay_Req Ingress Correction Field High Register (1588_RX_PDREQ_CF_HI_x)
1588 TX One-Step Sync Upper Seconds Register (1588_TX_ONE_STEP_SYNC_SEC)
1588 Port x RX Pdelay_Req Ingress Correction Field Low Register (1588_RX_PDREQ_CF_LOW_x)
1588 Port x RX Checksum Dropped Count Register (1588_RX_CHKSUM_DROPPED_CNT_x)
1588 Port x RX Filtered Count Register (1588_RX_FILTERED_CNT_x)
Switch Registers
Port 1 Manual Flow Control Register (MANUAL_FC_1)
Port 2 Manual Flow Control Register (MANUAL_FC_2)
Port 0 Manual Flow Control Register (MANUAL_FC_0)
Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA)
Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD)
EEPROM/LED Registers
EEPROM Command Register (E2P_CMD)
EEPROM Data Register (E2P_DATA)
LED Configuration Register (LED_CFG)
Virtual PHY 0 Registers
Port x Virtual PHY Basic Control Register (VPHY_BASIC_CTRL_x) x=0
Port x Virtual PHY Basic Status Register (VPHY_BASIC_STATUS_x) x=0
Port x Virtual PHY Identification MSB Register (VPHY_ID_MSB_x) x=0
Port x Virtual PHY Identification LSB Register (VPHY_ID_LSB_x) x=0
Port x Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV_x) x=0
Port x Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register
(VPHY_AN_LP_BASE_ABILITY_x) x=0
Port x Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP_x) x=0
Port x Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS_x) x=0
GPIO Registers
General Purpose I/O Configuration Register (GPIO_CFG)
General Purpose I/O Data & Direction Register (GPIO_DATA_DIR)
General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)
Switch Fabric MAC Address Registers
Switch Fabric MAC Address High Register (SWITCH_MAC_ADDRH)
Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL)
Reset Register
Reset Control Register (RESET_CTL)
 2015 Microchip Technology Inc.
DS00001925A-page 45