LAN9353 Datasheet, PDF (54/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
• Virtual PHY 1 Reset
• Switch Reset
• 1588 Reset
Port A PHY Reset
A Port A PHY reset is performed by setting the PHY_A_RST bit of the Reset Control Register (RESET_CTL) or the Soft
Reset bit in the PHY x Basic Control Register (PHY_BASIC_CONTROL_x). Upon completion of the Port A PHY reset,
the PHY_A_RST and Soft Reset bits are automatically cleared. No other modules of the device are affected by this
reset.
Port A PHY reset completion can be determined by polling the PHY_A_RST bit in the Reset Control Register
(RESET_CTL) or the Soft Reset bit in the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) until it clears.
Under normal conditions, the PHY_A_RST and Soft Reset bit will clear approximately 102 uS after the Port A PHY reset
occurrence.
Note: When using the Soft Reset bit to reset the Port A PHY, register bits designated as NASR are not reset.
In addition to the methods above, the Port A PHY is automatically reset after returning from a PHY power-down mode.
This reset differs in that the PHY power-down mode reset does not reload or reset any of the PHY registers. Refer to
Section 9.2.10, "PHY Power-Down Modes," on page 108 for additional information.
Refer to Section 9.2.13, "Resets," on page 113 for additional information on Port A PHY resets.
Port B PHY Reset
A Port B PHY reset is performed by setting the PHY_B_RST bit of the Reset Control Register (RESET_CTL) or the Soft
Reset bit in the PHY x Basic Control Register (PHY_BASIC_CONTROL_x). Upon completion of the Port B PHY reset,
the PHY_B_RST and Soft Reset bits are automatically cleared. No other modules of the device are affected by this
reset.
Port B PHY reset completion can be determined by polling the PHY_B_RST bit in the Reset Control Register
(RESET_CTL) or the Soft Reset bit in the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) until it clears.
Under normal conditions, the PHY_B_RST and Soft Reset bit will clear approximately 102 us after the Port B PHY reset
occurrence.
Note: When using the Soft Reset bit to reset the Port B PHY, register bits designated as NASR are not reset.
In addition to the methods above, the Port B PHY is automatically reset after returning from a PHY power-down mode.
This reset differs in that the PHY power-down mode reset does not reload or reset any of the PHY registers. Refer to
Section 9.2.10, "PHY Power-Down Modes," on page 108 for additional information.
Refer to Section 9.2.13, "Resets," on page 113 for additional information on Port B PHY resets.
Virtual PHY 0 Reset
A Virtual PHY reset is performed by setting the Virtual PHY 0 Reset (VPHY_0_RST) bit of the Reset Control Register
(RESET_CTL) or Reset in the Port x Virtual PHY Basic Control Register (VPHY_BASIC_CTRL_x). No other modules
of the device are affected by this reset.
Virtual PHY reset completion can be determined by polling the VPHY_0_RST bit in the Reset Control Register
(RESET_CTL) or the Reset bit in the Port x Virtual PHY Basic Control Register (VPHY_BASIC_CTRL_x) until it clears.
Under normal conditions, the VPHY_0_RST and Reset bit will clear approximately 1 us after the Virtual PHY reset
occurrence.
Refer to Section 9.3.3, "Virtual PHY Resets," on page 183 for additional information on Virtual PHY resets.
Virtual PHY 1 Reset
A Virtual PHY reset is performed by setting the VPHY_1_RST bit of the Reset Control Register (RESET_CTL) or Reset
in the Port x Virtual PHY Basic Control Register (VPHY_BASIC_CTRL_x). No other modules of the device are affected
by this reset.
DS00001925A-page 54
 2015 Microchip Technology Inc.