LAN9353 Datasheet, PDF (383/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

14.3.4 PMI TIMING REQUIREMENTS
FIGURE 14-2:
PMI TIMING
MDC
t_val
t_ohold
MDIO
(Data-Out)
t_clkp
t_clkh t_clkl
t_ohold
MDIO
(Data-In)
LAN9353
t_su t_ihold
TABLE 14-4: PMI TIMING VALUES
Symbol
t_clkp
t_clkh
t_clkl
t_val
t_ohold
t_su
t_ihold
Description
MDC period
MDC high time
MDC low time
MDIO output valid from rising edge of MDC
MDIO output hold from rising edge of MDC
MDIO input setup time to rising edge of MDC
MDIO input hold time after rising edge of MDC
Min
400
180 (90%)
180 (90%)
-
50
70
0
Max
-
-
-
250
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
Note 8: The PMI design outputs a nominal 400 ns clock with a 50/50 duty cycle.
Note 9: The PMI design changes output data a nominal 120 ns following the rising edge of MDC.
Note 10: The PMI design samples input data a nominal 40 ns prior to the rising edge of MDC.
Notes
Note 8
Note 8
Note 8
Note 9
Note 9
Note 10
Note 10
 2015 Microchip Technology Inc.
DS00001925A-page 383