LAN9353 Datasheet, PDF (26/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 3-6: SWITCH PORT 0 MII/RMII & CONFIGURATION STRAP PIN DESCRIPTIONS
Num
Pins
Name
Symbol
Buffer
Type
VIS/
VO12/
VO16
(PD)
Note 6
Description
RMII MAC Mode: This pin is an input or an output
running at 50 MHz and is used as the reference
clock for the P0_IND[1:0], P0_INDV, P0_OUTD[1:0],
and P0_OUTDV pins. The choice of input verses
output is based on the setting of the RMII Clock
Direction bit in the Port 0 Port x Virtual PHY Special
Control/Status Register (VPHY_SPECIAL_CON-
TROL_STATUS_x). A low selects P0_OUTCLK as
an input and a high selects P0_OUTCLK as an out-
put.
As an input, the pull-down is enabled by default.
Port 0 RMII
Reference Clock
1
(cont.)
P0_REFCLK
VIS/
VO12/
VO16
(PD)
Note 6
As an output, the input buffer and pull-down are dis-
abled. The choice of drive strength is based on the
MII Virtual PHY RMII/Turbo MII Clock Strength bit. A
low selects a 12 mA drive, while a high selects a
16 mA drive.
RMII PHY Mode: This pin is an input or an output
running at 50 MHz and is used as the reference
clock for the P0_IND[1:0], P0_INDV, P0_OUTD[1:0],
and P0_OUTDV pins. The choice of input verses
output is based on the setting of the RMII Clock
Direction bit in the Port 0 Port x Virtual PHY Special
Control/Status Register (VPHY_SPECIAL_CON-
TROL_STATUS_x). A low selects P0_OUTCLK as
an input and a high selects P0_OUTCLK as an out-
put.
As an input, the pull-down is normally enabled. The
input buffer and pull-down are disabled when the
Isolate (VPHY_ISO) bit is set in the Port 0 Port x Vir-
tual PHY Basic Control Register (VPHY_BASIC_C-
TRL_x).
Port 0 Mode[0]
Configuration
Strap
P0_MODE0
VIS
(PU)
Note 8
As an output, the input buffer and pull-down are dis-
abled. The choice of drive strength is based on the
MII Virtual PHY RMII/Turbo MII Clock Strength bit. A
low selects a 12 mA drive, while a high selects a
16 mA drive. The output driver is disabled when the
Isolate (VPHY_ISO) bit is set in the Port 0 Port x Vir-
tual PHY Basic Control Register (VPHY_BASIC_C-
TRL_x).
This strap configures the mode for Port 0. See
Note 7.
Refer to Table 7-3, “Port 0 Mode Strap Mapping,” on
page 83 for the Port 0 strap settings.
DS00001925A-page 26
 2015 Microchip Technology Inc.