LAN9353 Datasheet, PDF (265/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.7.2.11 Port x MAC Receive OK Count Register (MAC_RX_PKTOK_CNT_x)
Register #:
Port0: 0418h
Port1: 0818h
Port2: 0C18h
Size:
32 bits
This register provides a counter of received packets that are or proper length and are free of errors. The counter is
cleared upon being read.
Bits
Description
31:0 RX OK
Count of packets that are of proper length and are free of errors.
Note: This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100 Mbps is approximately 481 hours.
Type
RC
Default
00000000h
Note: A bad packet is one that has a FCS or Symbol error.
10.7.2.12 Port x MAC Receive CRC Error Count Register (MAC_RX_CRCERR_CNT_x)
Register #:
Port0: 0419h
Port1: 0819h
Port2: 0C19h
Size:
32 bits
This register provides a counter of received packets that with CRC errors. The counter is cleared upon being read.
Bits
Description
31:0 RX CRC
Count of packets that have between 64 and the maximum allowable number
of bytes and have a bad FCS, but do not have an extra nibble. The max num-
ber of bytes is 1518 for untagged packets and 1522 for tagged packets. If the
Jumbo2K bit is set in the Port x MAC Receive Configuration Register
(MAC_RX_CFG_x), the max number of bytes is 2048.
Note: This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100 Mbps is approximately 137 hours.
Type
RC
Default
00000000h
 2015 Microchip Technology Inc.
DS00001925A-page 265