LAN9353 Datasheet, PDF (337/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.7.4.25 Buffer Manager Port 2 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_2)
Register #:
1C18h
Size:
32 bits
This register counts the number of packets received on Port 2 that were dropped by the Buffer Manager due to ingress
rate limit discarding (Red and random Yellow dropping).
Bits
Description
31:0 Dropped Count
These bits count the number of dropped packets received on Port 2 and is
cleared when read.
Note: This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100 Mbps is approximately 481 hours.
10.7.4.26 Buffer Manager Interrupt Mask Register (BM_IMR)
Type
RC
Default
00000000h
Register #:
1C20h
Size:
32 bits
This register contains the Buffer Manager interrupt mask, which masks the interrupts in the Buffer Manager Interrupt
Pending Register (BM_IPR). All Buffer Manager interrupts are masked by setting the Interrupt Mask bit. Clearing this
bit will unmask the interrupts. Refer to Section 8.0, "System Interrupts," on page 84 for more information.
Bits
Description
31:1 RESERVED
0
Interrupt Mask
When set, this bit masks interrupts from the Buffer Manager. The status bits
in the Buffer Manager Interrupt Pending Register (BM_IPR) are not affected.
Type
RO
R/W
Default
-
1b
 2015 Microchip Technology Inc.
DS00001925A-page 337