LAN9353 Datasheet, PDF (9/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
FIGURE 2-1:
INTERNAL BLOCK DIAGRAM
LAN9353
Ethernet
Ethernet
10/100 PHY
w/fiber
w/802.3az
Registers
10/100 PHY
w/fiber
w/802.3az
Registers
PHY/RMII
Mux
RMII
Configuration
MII / RMII
Configuration
Virtual PHY
MAC to
MAC
Registers
Configuration
Virtual PHY
MAC to
MAC
Registers
Configuration
IEEE
1588v2
Time
Stamp
10/100
MAC
w/
802.3az
1588 Transparent Clocking
Switch Engine
Search
Engine
Buffer Manager
Frame
Buffers
Switch
Registers
(CSRs)
10/100
MAC
w/
802.3az
10/100
MAC
w/
802.3az
Switch Fabric
EEPROM
Loader
Register
Access
Mux
I²C
EEPROM
I²C Slave
PIN
Mux
To MII/RMII/
Turbo MII,
SMI, I2C
SMI Slave
Controller
Configuration
GPIO/LED
Controller
IEEE 1588v2
Clock/Events
System
Interrupt
Controller
System _{GP Timer}
Clocks/
Reset/PME _Free-Run
Controller Clk
To optional GPIOs/LEDs
IRQ
External
25MHz Crystal
 2015 Microchip Technology Inc.
DS00001925A-page 9