LAN9353 Datasheet, PDF (154/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
MDIO Manageable Device (MMD) Registers
The device MMD registers adhere to the IEEE 802.3-2008 45.2 MDIO Interface Registers specification. The MMD reg-
isters are not memory mapped. These registers are accessed indirectly via the PHY x MMD Access Control Register
(PHY_MMD_ACCESS) and PHY x MMD Access Address/Data Register (PHY_MMD_ADDR_DATA). The supported
MMD device addresses are 3 (PCS), 7 (Auto-Negotiation), and 30 (Vendor Specific). Table 9-19, "MMD Registers"
details the supported registers within each MMD device.
TABLE 9-19: MMD REGISTERS
MMD DEVICE
ADDRESS
(IN DECIMAL)
INDEX
(IN DECIMAL)
0
1
5
6
3
(PCS)
20
22
32784
32785
32786
32801
32802
32803
32804
32805
32806
32807
32808
32865
32866
32867
5
6
7
(Auto-Negotiation)
60
61
REGISTER NAME
PHY x PCS Control 1 Register (PHY_PCS_CTL1_x)
PHY x PCS Status 1 Register (PHY_PCS_STAT1_x)
PHY x PCS MMD Devices Present 1 Register (PHY_PCS_MMD_PRE-
SENT1_x)
PHY x PCS MMD Devices Present 2 Register (PHY_PCS_MMD_PRE-
SENT2_x)
PHY x EEE Capability Register (PHY_EEE_CAP_x)
PHY x EEE Wake Error Register (PHY_EEE_WAKE_ERR_x)
PHY x Wakeup Control and Status Register (PHY_WUCSR_x)
PHY x Wakeup Filter Configuration Register A (PHY_WUF_CFGA_x)
PHY x Wakeup Filter Configuration Register B (PHY_WUF_CFGB_x)
PHY x Wakeup Filter Byte Mask Registers (PHY_WUF_MASK_x)
PHY x MAC Receive Address A Register (PHY_RX_ADDRA_x)
PHY x MAC Receive Address B Register (PHY_RX_ADDRB_x)
PHY x MAC Receive Address C Register (PHY_RX_ADDRC_x)
PHY x Auto-Negotiation MMD Devices Present 1 Register
(PHY_AN_MMD_PRESENT1_x)
PHY x Auto-Negotiation MMD Devices Present 2 Register
(PHY_AN_MMD_PRESENT2_x)
PHY x EEE Advertisement Register (PHY_EEE_ADV_x)
PHY x EEE Link Partner Advertisement Register (PHY_EEE_LP_AD-
V_x)
DS00001925A-page 154
 2015 Microchip Technology Inc.