LAN9353 Datasheet, PDF (319/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.7.3.36 Switch Engine Port 2 Ingress VLAN Priority Regeneration Table Register
(SWE_INGRSS_REGEN_TBL_2)
Register #:
1857h
Size:
32 bits
This register provides the ability to map the received VLAN priority to a regenerated priority. The regenerated priority is
used in determining the output priority queue. By default, the regenerated priority is identical to the received priority.
Bits
Description
31:24
23:21
RESERVED
Regen7
These bits specify the regenerated priority for received priority 7.
20:18 Regen6
These bits specify the regenerated priority for received priority 6.
17:15 Regen5
These bits specify the regenerated priority for received priority 5.
14:12 Regen4
These bits specify the regenerated priority for received priority 4.
11:9 Regen3
These bits specify the regenerated priority for received priority 3.
8:6 Regen2
These bits specify the regenerated priority for received priority 2.
5:3 Regen1
These bits specify the regenerated priority for received priority 1.
2:0 Regen0
These bits specify the regenerated priority for received priority 0.
Type
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
-
111b
110b
101b
100b
011b
010b
001b
000b
10.7.3.37 Switch Engine Port 0 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_0)
Register #:
1858h
Size:
32 bits
This register counts the number of MAC addresses on Port 0 that were not learned or were overwritten by a different
address due to address table space limitations.
Bits
Description
31:0 Learn Discard
This field is a count of MAC addresses not learned or overwritten and is
cleared when read.
Note: This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100 Mbps is approximately 481 hours.
Type
RC
Default
00000000h
 2015 Microchip Technology Inc.
DS00001925A-page 319