LAN9353 Datasheet, PDF (69/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 7-1: SOFT-STRAP CONFIGURATION STRAP DEFINITIONS (CONTINUED)
Strap Name
autoneg_strap_1
Description
Pin / Default Value
PHY A Auto Negotiation Enable Strap: Configures the
default value of the Auto-Negotiation Enable (PHY_AN)
enable bit in the (x=A) PHY x Basic Control Register
(PHY_BASIC_CONTROL_x).
1b when in internal
PHY mode
(P1_INTPHY=1)
else 0b
This strap also affects the default value of the following regis-
ter bits (x=A):
• Speed Select LSB (PHY_SPEED_SEL_LSB) and Duplex
Mode (PHY_DUPLEX) bits of the PHY x Basic Control
Register (PHY_BASIC_CONTROL_x)
• 10BASE-T Full Duplex and 10BASE-T Half Duplex bits of
the PHY x Auto-Negotiation Advertisement Register
(PHY_AN_ADV_x)
• PHY Mode (MODE[2:0]) bits of the PHY x Special Modes
Register (PHY_SPECIAL_MODES_x)
Note: This has no effect when the PHY is in 100BASE-FX
mode.
Refer to the respective register definition sections for addi-
tional information.
speed_strap_1
PHY A Speed Select Strap: This strap affects the default
1b
Note: speed_strap_1 and ^{value of the following register bits (x=A):}
speed_pol_strap_1 share
the same strap register and ^{• Speed Select LSB (PHY_SPEED_SEL_LSB) bit of the}
EEPROM bit.
PHY x Basic Control Register (PHY_BASIC_CON-
TROL_x)
• 10BASE-T Full Duplex and 10BASE-T Half Duplex bits of
the PHY x Auto-Negotiation Advertisement Register
(PHY_AN_ADV_x)
• PHY Mode (MODE[2:0]) bits of the PHY x Special Modes
Register (PHY_SPECIAL_MODES_x)
Note: This has no effect when the PHY is in 100BASE-FX
mode.
Refer to the respective register definition sections for addi-
tional information.
 2015 Microchip Technology Inc.
DS00001925A-page 69