LAN9353 Datasheet, PDF (411/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
Host must maintain the 1588 TX One-Step Sync Upper Seconds Register (1588_TX_ONE_STEP_SYNC_SEC). The
Host should avoid sending a Sync message if there is a possibility that the 32-bit seconds counter will reach its rollover
value before the message is transmitted.
A 32-bit sub-nanoseconds counter is used to precisely tune the rate of the 1588 Clock by accounting for the difference
between the nominal 10ns and the actual rate of the master clock. Every reference clock period the sub-nanoseconds
counter is incremented by the Clock Rate Adjustment Value (1588_CLOCK_RATE_ADJ_VALUE) in the 1588 Clock
Rate Adjustment Register (1588_CLOCK_RATE_ADJ), specified in 2^-32 nanoseconds. When the sub-nanoseconds
counter rolls over past zero, the nanoseconds portion of the 1588 Clock is incremented by 9 or 11 instead of the normal
value of 10. The choice to speed up or slow down is determined by the Clock Rate Adjustment Direction
(1588_CLOCK_RATE_ADJ_DIR) bit. The ability to adjust for 1 ns approximately every 43 seconds allows for a tuning
precision of approximately 2.3^-9 percent. The maximum adjustment is 1 ns every 4 clocks (40 ns) or 2.5 percent.
In addition to adjusting the frequency of the 1588 Clock, the Host may directly set the 1588 Clock, make a one-time step
adjustment of the 1588 Clock or specify a temporary rate. The choice of method depends on needed adjustment. For
initial adjustments, direct or one-time step adjustments may be best. For on-going minor adjustments, the temporary
rate adjustment may be best. Ideally, the frequency will be matched and once the 1588 Clock is synchronized, no further
adjustments would be needed.
In order to perform a direct writing of the 1588 Clock, the desired value is written into the 1588 Clock Seconds Register
(1588_CLOCK_SEC), 1588 Clock NanoSeconds Register (1588_CLOCK_NS) and 1588 Clock Sub-NanoSeconds
Register (1588_CLOCK_SUBNS). The Clock Load (1588_CLOCK_LOAD) bit in the 1588 Command and Control Reg-
ister (1588_CMD_CTL) is then set.
In order to perform a one-time positive or negative adjustment to the seconds portion of the 1588 Clock, the desired
change and direction are written into the 1588 Clock Step Adjustment Register (1588_CLOCK_STEP_ADJ). The Clock
Step Seconds (1588_CLOCK_STEP_SECONDS) bit in the 1588 Command and Control Register (1588_CMD_CTL) is
then set. The internal sub-nanoseconds counter and the nanoseconds portion of the 1588 Clock are not affected. If a
nanoseconds portion rollover coincides with the 1588 Clock adjustment, the 1588 Clock adjustment is applied in addi-
tion to the seconds increment.
In order to perform a one-time positive adjustment to the nanoseconds portion of the 1588 Clock, the desired change
is written into the 1588 Clock Step Adjustment Register (1588_CLOCK_STEP_ADJ). The Clock Step NanoSeconds
(1588_CLOCK_STEP_NANOSECONDS) bit in the 1588 Command and Control Register (1588_CMD_CTL) is then
set. If the addition to the nanoseconds portion results in a rollover past zero, then the seconds portion of the 1588 Clock
is incremented. The normal (9, 10 or 11 ns) increment to the nanoseconds portion is suppressed for one clock. This can
be compensated for by specifying an addition value 10ns higher. A side benefit is that using an addition value of 0 effec-
tively pauses the 1588 Clock for 10ns while a value less than 10 slows the clock down just briefly. The internal sub-
nanoseconds counter of the 1588 Clock is not affected by the adjustment, however, if a sub-nanoseconds counter roll-
over coincides with the 1588 Clock adjustment it will be missed.
In order to perform a temporary rate adjustment of the 1588 Clock, the desired temporary rate and direction are written
into the 1588 Clock Temporary Rate Adjustment Register (1588_CLOCK_TEMP_RATE_ADJ) and the duration of the
temporary rate, specified in reference clock cycles, is written into the 1588 Clock Temporary Rate Duration Register
(1588_CLOCK_TEMP_RATE_DURATION). The Clock Temporary Rate (1588_CLOCK_TEMP_RATE) bit in the 1588
Command and Control Register (1588_CMD_CTL) is then set. Once the temporary rate duration expires, the Clock
Temporary Rate (1588_CLOCK_TEMP_RATE) bit will self-clear and the 1588 Clock Rate Adjustment Register
(1588_CLOCK_RATE_ADJ) will once again control the 1588 Clock rate. This method of adjusting the 1588 Clock may
be preferred since it avoids large discrete changes in the 1588 Clock value. For a maximum setting in both the 1588
Clock Temporary Rate Adjustment Register (1588_CLOCK_TEMP_RATE_ADJ) and 1588 Clock Temporary Rate Dura-
tion Register (1588_CLOCK_TEMP_RATE_DURATION), the 1588 Clock can be adjusted by approximately 1 second.
 2015 Microchip Technology Inc.
DS00001925A-page 411