LAN9353 Datasheet, PDF (481/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
16.0 GENERAL PURPOSE TIMER & FREE-RUNNING CLOCK
This chapter details the General Purpose Timer (GPT) and the Free-Running Clock.
16.1 General Purpose Timer
The device provides a 16-bit programmable General Purpose Timer that can be used to generate periodic system inter-
rupts. The resolution of this timer is 100 µs.
The GPT loads the General Purpose Timer Count Register (GPT_CNT) with the value in the General Purpose Timer
Pre-Load (GPT_LOAD) field of the General Purpose Timer Configuration Register (GPT_CFG) when the General Pur-
pose Timer Enable (TIMER_EN) bit of the General Purpose Timer Configuration Register (GPT_CFG) is asserted (1).
On a chip-level reset or when the General Purpose Timer Enable (TIMER_EN) bit changes from asserted (1) to de-
asserted (0), the General Purpose Timer Pre-Load (GPT_LOAD) field is initialized to FFFFh. The General Purpose
Timer Count Register (GPT_CNT) is also initialized to FFFFh on reset.
Once enabled, the GPT counts down until it reaches 0000h. At 0000h, the counter wraps around to FFFFh, asserts the
GP Timer (GPT_INT) interrupt status bit in the Interrupt Status Register (INT_STS), asserts the IRQ interrupt (if GP
Timer Interrupt Enable (GPT_INT_EN) is set in the Interrupt Enable Register (INT_EN)) and continues counting. GP
Timer (GPT_INT) is a sticky bit. Once this bit is asserted, it can only be cleared by writing a 1 to the bit. Refer to Section
8.2.6, "General Purpose Timer Interrupt," on page 87 for additional information on the GPT interrupt.
Software can write a pre-load value into the General Purpose Timer Pre-Load (GPT_LOAD) field at any time (e.g.,
before or after the General Purpose Timer Enable (TIMER_EN) bit is asserted). The General Purpose Timer Count Reg-
ister (GPT_CNT) will immediately be set to the new value and continue to count down (if enabled) from that value.
16.2 Free-Running Clock
The Free-Running Clock (FRC) is a simple 32-bit up-counter that operates from a fixed 25 MHz clock. The current FRC
value can be read via the Free Running 25MHz Counter Register (FREE_RUN). On assertion of a chip-level reset, this
counter is cleared to zero. On de-assertion of a reset, the counter is incremented once for every 25 MHz clock cycle.
When the maximum count has been reached, the counter rolls over to zeros. The FRC does not generate interrupts.
Note: The free running counter can take up to 160 ns to clear after a reset event.
16.3 General Purpose Timer and Free-Running Clock Registers
This section details the directly addressable general purpose timer and free-running clock related System CSRs. For
an overview of the entire directly addressable register map, refer to Section 5.0, "Register Map," on page 41.
TABLE 16-1: MISCELLANEOUS REGISTERS
ADDRESS
08Ch
090h
09Ch
Register Name (SYMBOL)
General Purpose Timer Configuration Register (GPT_CFG)
General Purpose Timer Count Register (GPT_CNT)
Free Running 25MHz Counter Register (FREE_RUN)
 2015 Microchip Technology Inc.
DS00001925A-page 481