LAN9353 Datasheet, PDF (366/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
13.4 Switch Fabric Timing Requirements
The timing requirements shown below use the notation of Px_ to represent either port 0 or port 1.
Depending on the SKU, port 1 pins may not be applicable.
13.4.1 MII INTERFACE TIMING (MAC MODE)
This section specifies the MII interface input and output timing when in MAC mode.
FIGURE 13-1:
MII OUTPUT TIMING (MAC MODE)
Px_OUTCLK
(input)
Px_OUTD[3:0],
Px_OUTER
Px_OUTDV
t_clkp
t_clkh t_clkl
t_val
t_val
t_hold
t_hold
t_val
TABLE 13-1: MII OUTPUT TIMING VALUES (MAC MODE)
Symbol
t_clkp
t_clkh
t_clkl
t_val
t_hold
Description
Px_OUTCLK period
Px_OUTCLK high time
Px_OUTCLK low time
Px_OUTD[3:0], Px_OUTER, Px_OUTDV output
valid from rising edge of Px_OUTCLK
Px_OUTD[3:0], Px_OUTER, Px_OUTDV output
hold from rising edge of Px_OUTCLK
Min
40
t_clkp * 0.4
t_clkp * 0.4
-
0
Max
-
t_clkp * 0.6
t_clkp * 0.6
22.0
-
Units
ns
ns
ns
ns
ns
Note 1: Timing was designed for system load between 10 pF and 25 pF.
Notes
Note 1
Note 1
DS00001925A-page 366
 2015 Microchip Technology Inc.