LAN9353 Datasheet, PDF (77/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 7-1: SOFT-STRAP CONFIGURATION STRAP DEFINITIONS (CONTINUED)
Strap Name
Description
Pin / Default Value
speed_pol_strap_0
Switch Port 0 Speed Polarity Strap: This strap determines 1b
Note: speed_strap_0 and ^{the polarity of the P0_SPEED when in Port 0 RMII MAC}
speed_pol_strap_0 share ^mode.
the same strap register and
EEPROM bit.
0 = P0_SPEED low means 100Mbps, high means 10Mbps
1 = P0_SPEED high means 100Mbps, low means 10Mbps
Refer to the respective register definition sections for addi-
tional information.
duplex_strap_0
Port 0 Virtual PHY Duplex Select Strap: This strap affects 1b
Note: duplex_strap_0 and
duplex_pol_strap_0 share
the same strap register and
the default value of the following bits in the (x=0) Port x Virtual
PHY Auto-Negotiation Link Partner Base Page Ability Regis-
ter (VPHY_AN_LP_BASE_ABILITY_x):
EEPROM bit.
• 100BASE-X Full Duplex
• 100BASE-X Half Duplex
• 10BASE-T Full Duplex
• 10BASE-T Half Duplex
Refer to Section 9.3.5.6 and Table 9-23 for more information.
Refer to the respective register definition sections for addi-
tional information.
duplex_pol_strap_0
Switch Port 0 Duplex Polarity Strap: This strap determines 1b
Note: duplex_strap_0 and ^{the polarity of the P0_DUPLEX pin when in Port 0 MII MAC}
duplex_pol_strap_0 share ^{and RMII MAC modes.}
the same strap register and
EEPROM bit.
0 = P0_DUPLEX low means full-duplex
1 = P0_DUPLEX high means full-duplex
BP_EN_strap_0
Refer to the respective register definition sections for addi-
tional information.
Switch Port 0 Backpressure Enable Strap: Configures the 1b
default value of the Port 0 Backpressure Enable (BP_EN_0)
bit of the Port 0 Manual Flow Control Register (MANUAL_F-
C_0).
FD_FC_strap_0
Refer to the respective register definition sections for addi-
tional information.
Switch Port 0 Full-Duplex Flow Control Enable Strap: This 1b
strap is used to configure the default value of the following
register bits:
• Port 0 Full-Duplex Transmit Flow Control Enable (TX_F-
C_0) and Port 0 Full-Duplex Receive Flow Control Enable
(RX_FC_0) bits of the Port 0 Manual Flow Control Regis-
ter (MANUAL_FC_0)
Refer to the respective register definition sections for addi-
tional information.
 2015 Microchip Technology Inc.
DS00001925A-page 77