LAN9353 Datasheet, PDF (25/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 3-6: SWITCH PORT 0 MII/RMII & CONFIGURATION STRAP PIN DESCRIPTIONS
Num
Pins
Name
1
Port 0 MII
Output Clock
Symbol
P0_OUTCLK
Buffer
Type
VIS
(PD)
VO12/
VO16
Note 6
Description
MII MAC Mode: This pin is an input and is used as
the reference clock for the P0_OUT[3:0],
P0_OUTDV and P0_OUTER pins. It is connected to
the transmit clock of the external PHY.
MII PHY Mode: This pin is an output and is used as
the reference clock for the P0_OUT[3:0] and
P0_OUTDV pins. It is connected to the receive clock
of the external MAC. The output driver is disabled
when the Isolate (VPHY_ISO) bit is set in the Port 0
Port x Virtual PHY Basic Control Register
(VPHY_BASIC_CTRL_x). When operating at
200 Mbps, the choice of drive strength is based on
the setting of the RMII/Turbo MII Clock Strength bit
in the Port 0 Port x Virtual PHY Special Control/Sta-
tus Register (VPHY_SPECIAL_CONTROL_STA-
TUS_x). A low selects a 12 mA drive, while a high
selects a 16 mA drive.
 2015 Microchip Technology Inc.
DS00001925A-page 25