LAN9353 Datasheet, PDF (50/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
6.0 CLOCKS, RESETS, AND POWER MANAGEMENT
6.1 Clocks
The device provides generation of all system clocks as required by the various sub-modules of the device. The clocking
sub-system is comprised of the following:
• Crystal Oscillator
• PHY PLL
6.1.1 CRYSTAL OSCILLATOR
The device requires a fixed-frequency 25 MHz clock source for use by the internal clock oscillator and PLL. This is typ-
ically provided by attaching a 25 MHz crystal to the OSCI and OSCO pins as specified in Section 20.7, "Clock Circuit,"
on page 515. Optionally, this clock can be provided by driving the OSCI input pin with a single-ended 25 MHz clock
source. If a single-ended source is selected, the clock input must run continuously for normal device operation. Power
savings modes allow for the oscillator or external clock input to be halted.
The crystal oscillator can be disabled as describe in Section 6.3.4, "Chip Level Power Management," on page 60.
For system level verification, the crystal oscillator output can be enabled onto the IRQ pin. See Section 8.2.9, "Clock
Output Test Mode," on page 88.
Power for the crystal oscillator is provided by a dedicated regulator or separate input pin. See Section 4.1.2, "1.2 V Crys-
tal Oscillator Regulator," on page 40.
Note: Crystal specifications are provided in Table 20-13, “Crystal Specifications,” on page 515.
6.1.2 PHY PLL
The PHY module receives the 25 MHz reference clock and, in addition to its internal clock usage, outputs a main system
clock that is used to derive device sub-system clocks.
The PHY PLL can be disabled as describe in Section 6.3.4, "Chip Level Power Management," on page 60. The PHY
PLL will be disabled only when requested and if the PHY ports are in a power down mode.
Power for PHY PLL is provided by an external input pin, usually sourced by the device’s 1.2V core regulator. See Section
4.0, "Power Connections," on page 38.
DS00001925A-page 50
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