LAN9353 Datasheet, PDF (324/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.7.4.2 Buffer Manager Drop Level Register (BM_DROP_LVL)
Register #:
1C01h
This register configures the overall buffer usage limits.
Size:
32 bits
Bits
Description
31:16
15:8
RESERVED
Drop Level Low
These bits specify the buffer limit that can be used per ingress port during
times when 2 or 3 ports are active.
Each buffer is 128 bytes.
Note: A port is “active” when 36 buffers are in use for that port.
7:0 Drop Level High
These bits specify the buffer limit that can be used per ingress port during
times when 1 port is active.
Each buffer is 128 bytes.
Note: A port is “active” when 36 buffers are in use for that port.
Type
RO
R/W
R/W
10.7.4.3 Buffer Manager Flow Control Pause Level Register (BM_FC_PAUSE_LVL)
Register #:
1C02h
Size:
32 bits
This register configures the buffer usage level when a Pause frame or backpressure is sent.
Default
-
49h
64h
Bits
Description
31:16
15:8
RESERVED
Pause Level Low
These bits specify the buffer usage level during times when 2 or 3 ports are
active.
Each buffer is 128 bytes.
Note: A port is “active” when 36 buffers are in use for that port.
7:0 Pause Level High
These bits specify the buffer usage level during times when 1 port is active.
Each buffer is 128 bytes.
Note: A port is “active” when 36 buffers are in use for that port.
Type
RO
R/W
R/W
Default
-
21h
3Ch
DS00001925A-page 324
 2015 Microchip Technology Inc.