LAN9353 Datasheet, PDF (60/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
6.3.3.2 Disabling The 1588 Unit
The entire 1588 Unit, including the CSRs, may be disabled by setting the 1588_DIS bit in the Power Management Con-
trol Register (PMT_CTRL). As a safety precaution, in order for this bit to be set, it must be written as a 1 two consecutive
times. A write of a 0 will reset the count.
Individual Timestamp Units, including their local CSRs, may be disabled by setting the appropriate 1588_TSU_x_DIS
bit in the Power Management Control Register (PMT_CTRL). As a safety precaution, in order for a bit to be set, it must
be written as a 1 two consecutive times. A write of a 0 will reset the count.
6.3.3.3 PHY Power Down
A PHY may be placed into power-down as described in Section 9.2.10, "PHY Power-Down Modes," on page 108.
6.3.3.4 LED Pins Power Down
All LED outputs may be disabled by setting the LED_DIS bit in the Power Management Control Register (PMT_CTRL).
Open-drain / open-source LEDs are un-driven. Push-pull LEDs are still driven but are set to their inactive state.
APPLICATION NOTE: Individual LEDs can be disabled by setting them open-drain GPIO outputs with a data value
of 1.
6.3.4 CHIP LEVEL POWER MANAGEMENT
The device supports power-down modes to allow applications to minimize power consumption.
Power is reduced by disabling the clocks as outlined in Table 6-2, "Power Management States". All configuration data
is saved when in any power state. Register contents are not affected unless specifically indicated in the register descrip-
tion.
There is one normal operating power state, D0, and three power saving states: D1, D2 and D3. Although appropriate
for various wake-up detection functions, the power states do not directly enable and are not enforced by these functions.
D0: Normal Mode - This is the normal mode of operation of this device. In this mode, all functionality is available.
This mode is entered automatically on any chip-level reset (POR, RST# pin reset).
D1: System Clocks Disabled, XTAL, PLL and network clocks enabled - In this low power mode, all clocks derived
from the PLL clock are disabled. The network clocks remain enabled if supplied by the PHYs or externally. The
crystal oscillator and the PLL remain enabled. Exit from this mode may be done manually or automatically.
This mode could be used for PHY General Power Down mode, PHY WoL mode and PHY Energy Detect Power
Down mode.
D2: System Clocks Disabled, PLL disable requested, XTAL enabled - In this low power mode, all clocks derived
from the PLL clock are disabled. The PLL is allowed to be disabled (and will disable if both of the PHYs are in
either Energy Detect or General Power Down). The network clocks remain enabled if supplied by the PHYs or
externally. The crystal oscillator remains enabled. Exit from this mode may be done manually or automatically.
This mode is useful for PHY Energy Detect Power Down mode and PHY WoL mode. This mode could be used
for PHY General Power Down mode.
D3: System Clocks Disabled, PLL disabled, XTAL disabled - In this low power mode, all clocks derived from the
PLL clock are disabled. The PLL will be disabled. External network clocks are gated off. The crystal oscillator is
disabled. Exit from this mode may be only be done manually.
This mode is useful for PHY General Power Down mode.
The Host must place the PHYs into General Power Down mode by setting the Power Down (PHY_PWR_DWN)
bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) before setting this power state.
TABLE 6-2: POWER MANAGEMENT STATES
Clock Source
25 MHz Crystal Oscillator
PLL
system clocks (100 MHz, 50 MHz, 25 MHz and others)
network clocks
D0
ON
ON
ON
available(1)
D1
ON
ON
OFF
available(1)
D2
ON
OFF(2)
OFF
available(1)
D3
OFF
OFF
OFF
OFF(3)
DS00001925A-page 60
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