LAN9353 Datasheet, PDF (494/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
17.4.4
GENERAL PURPOSE I/O INTERRUPT STATUS AND ENABLE REGISTER
(GPIO_INT_STS_EN)
Offset:
1E8h
Size:
32 bits
This read/write register contains the GPIO interrupt status bits.
Writing a 1 to any of the interrupt status bits acknowledges and clears the interrupt. If enabled, these interrupt bits are
cascaded into the GPIO Interrupt Event (GPIO) bit of the Interrupt Status Register (INT_STS). Writing a 1 to any of the
interrupt enable bits will enable the corresponding interrupt as a source. Status bits will still reflect the status of the inter-
rupt source regardless of whether the source is enabled as an interrupt in this register. The GPIO Interrupt Event Enable
(GPIO_EN) bit of the Interrupt Enable Register (INT_EN) must also be set in order for an actual system level interrupt
to occur. Refer to Section 8.0, "System Interrupts," on page 84 for additional information.
BITS
DESCRIPTION
31:24
23:16
15:8
7:0
RESERVED
GPIO Interrupt Enable[7:0] (GPIO[7:0]_INT_EN)
When set, these bits enable the corresponding GPIO interrupt.
Note:
The GPIO interrupts must also be enabled via the GPIO Interrupt
Event Enable (GPIO_EN) bit of the Interrupt Enable Register
(INT_EN) in order to cause the interrupt pin (IRQ) to be asserted.
RESERVED
GPIO Interrupt[7:0] (GPIO[7:0]_INT)
These signals reflect the interrupt status as generated by the GPIOs. These
interrupts are configured through the General Purpose I/O Configuration
Register (GPIO_CFG).
Note: As GPIO interrupts, GPIO inputs are level sensitive and must be
active greater than 40 ns to be recognized as interrupt inputs.
TYPE
RO
R/W
RO
R/WC
DEFAULT
-
00h
-
00h
DS00001925A-page 494
 2015 Microchip Technology Inc.