LAN9353 Datasheet, PDF (257/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.7.1.3 Switch Global Interrupt Mask Register (SW_IMR)
Register #:
0004h
Size:
32 bits
This read/write register contains the global interrupt mask for the Switch Fabric interrupts. All switch related interrupts
in the Switch Global Interrupt Pending Register (SW_IPR) may be masked via this register. An interrupt is masked by
setting the corresponding bit of this register. Clearing a bit will unmask the interrupt. When an unmasked Switch Fabric
interrupt is generated in the Switch Global Interrupt Pending Register (SW_IPR), the interrupt will trigger the Switch Fab-
ric Interrupt Event (SWITCH_INT) bit in the Interrupt Status Register (INT_STS). Refer to Section 8.0, "System Inter-
rupts," on page 84 for more information.
Bits
Description
31:9 RESERVED
8:7 RESERVED
Note: These bits must be written as 11b.
6
Buffer Manager Interrupt Mask (BM)
When set, prevents the generation of Switch Fabric interrupts due to the Buf-
fer Manager via the Buffer Manager Interrupt Pending Register (BM_IPR).
The status bits in the Switch Global Interrupt Pending Register (SW_IPR) are
not affected.
5
Switch Engine Interrupt Mask (SWE)
When set, prevents the generation of Switch Fabric interrupts due to the
Switch Engine via the Switch Engine Interrupt Pending Register (SWE_IPR).
The status bits in the Switch Global Interrupt Pending Register (SW_IPR) are
not affected.
4:3 RESERVED
Note: These bits must be written as 11b.
2
Port 2 MAC Interrupt Mask (MAC_2)
When set, prevents the generation of Switch Fabric interrupts due to the Port
2 MAC via the MAC_IPR_2 register (see Section 10.7.2.50, on page 285).
The status bits in the Switch Global Interrupt Pending Register (SW_IPR) are
not affected.
1
Port 1 MAC Interrupt Mask (MAC_1)
When set, prevents the generation of Switch Fabric interrupts due to the Port
1 MAC via the MAC_IPR_1 register (see Section 10.7.2.50, on page 285).
The status bits in the Switch Global Interrupt Pending Register (SW_IPR) are
not affected.
0
Port 0 MAC Interrupt Mask (MAC_0)
When set, prevents the generation of Switch Fabric interrupts due to the Port
0 MAC via the MAC_IPR_0 register (see Section 10.7.2.50, on page 285).
The status bits in the Switch Global Interrupt Pending Register (SW_IPR) are
not affected.
Type
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
-
11b
1b
1b
11b
1b
1b
1b
 2015 Microchip Technology Inc.
DS00001925A-page 257