LAN9353 Datasheet, PDF (323/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.7.4 BUFFER MANAGER CSRS
This section details the Buffer Manager (BM) registers. These registers allow configuration and monitoring of the switch
buffer levels and usage. A list of the general switch CSRs and their corresponding register numbers is included in
Table 10-9.
10.7.4.1 Buffer Manager Configuration Register (BM_CFG)
Register #:
1C00h
Size:
This register enables egress rate pacing and ingress rate discarding.
32 bits
Bits
Description
31:7 RESERVED
6
BM Counter Test
When this bit is set, Buffer Manager (BM) counters that normally clear to 0
when read, will be set to 7FFF_FFFC when read.
5
Fixed Priority Queue Servicing
When set, output queues are serviced with a fixed priority ordering. When
cleared, output queues are serviced with a weighted round robin ordering.
4:2 Egress Rate Enable
When set, egress rate pacing is enabled. Bits 4,3,2 correspond to switch
ports 2,1,0 respectively.
1
Drop on Yellow
When this bit is set, packets that exceed the Ingress Committed Burst Size
(colored Yellow) are subjected to random discard.
Note:
See Section 10.7.3.27, "Switch Engine Ingress Rate Command
Register (SWE_INGRSS_RATE_CMD)," on page 313 for
information on configuring the Ingress Committed Burst Size.
0
Drop on Red
When this bit is set, packets that exceed the Ingress Excess Burst Size (col-
ored Red) are discarded.
Note:
See Section 10.7.3.27, "Switch Engine Ingress Rate Command
Register (SWE_INGRSS_RATE_CMD)," on page 313 for
information on configuring the Ingress Excess Burst Size.
Type
RO
R/W
R/W
R/W
R/W
R/W
Default
-
0b
0b
0b
0b
0b
 2015 Microchip Technology Inc.
DS00001925A-page 323