LAN9353 Datasheet, PDF (442/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
15.8.20 1588 PORT X ASYMMETRY AND PEER DELAY REGISTER (1588_ASYM_PEERDLY_X)
Offset:
Bank:
15Ch
0
Size:
32 bits
Note:
Port and GPIO registers share a common address space. Port registers are selected by the Bank Select
(BANK_SEL[2:0] in the 1588 Bank Port GPIO Select Register (1588_BANK_PORT_GPIO_SEL). The port
accessed (“x”) is set by the Port Select (PORT_SEL[1:0]) field.
Bits
Description
31:16 Port Delay Asymmetry (DELAY_ASYM[15:0])
This field specifies the previously known delay asymmetry in nanoseconds.
This is a signed 2’s complement number. Positive values occur when the
master-to-slave or responder-to-requestor propagation time is longer than
the slave-to-master or requestor-to-responder propagation time.
Note:
The host S/W must not change this field while the 1588 Enable
(1588_ENABLE) bit in 1588 Command and Control Register
(1588_CMD_CTL) is set.
15:0 RX Peer Delay (RX_PEER_DELAY[15:0])
This field specifies the measured peer delay in nanoseconds used during
peer-to-peer mode.
Type
R/W
R/W
Default
0000h
0000h
DS00001925A-page 442
 2015 Microchip Technology Inc.