LAN9353 Datasheet, PDF (193/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
9.3.5.4 Port x Virtual PHY Identification LSB Register (VPHY_ID_LSB_x)
Offset:
PORT0: 1CCh
PORT1: 0CCh
Index (decimal): 3
Size:
32 bits
16 bits
This read/write register contains the LSB of the Virtual PHY Organizationally Unique Identifier (OUI). The MSB of the
Virtual PHY OUI is contained in the Port x Virtual PHY Identification MSB Register (VPHY_ID_MSB_x).
BITS
DESCRIPTION
31:16 RESERVED
(See Note 47)
15:10 PHY ID
This field contains the lower 6-bits of the Virtual PHY OUI (Note 48).
9:4 Model Number
This field contains the 6-bit manufacturer’s model number of the Virtual PHY
(Note 48).
3:0 Revision Number
This field contain the 4-bit manufacturer’s revision number of the Virtual PHY
(Note 48).
TYPE
RO
R/W
R/W
R/W
DEFAULT
-
000000b
000000b
0000b
Note 47: The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a DWORD bound-
ary. When accessed serially (through the MII management protocol), the register is 16-bits wide.
Note 48: IEEE allows a value of zero in each of the 32-bits of the PHY Identifier.
 2015 Microchip Technology Inc.
DS00001925A-page 193