LAN9353 Datasheet, PDF (382/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
14.3 PHY Management Interface (PMI)
The PMI provides an parallel to serial interface used to access the internal Physical PHYs as well as the external PHYs
on the MII pins (in MAC modes).
14.3.1 PMI SLAVE COMMAND FORMAT
The PMI operates at 2.5 MHz and implements the IEEE 802.3 management protocol, providing read/write commands
for PHY configuration.
A read or write is performed using the frame format shown in Table 14-3. All addresses and data are transferred MSB
first. Data bytes are transferred little endian.
TABLE 14-3: MII MANAGEMENT FRAME FORMAT
Preamble
READ
WRITE
32 1’s
32 1’s
Start
01
01
Op
PHY
Code Address
10
AAAAA
01
AAAAA
Register
Address
RRRRR
RRRRR
Turn-
Around
Time
Note 6
Z0
10
Data
Idle
Note 7
DDDDDDDDDDDDDDDD
Z
DDDDDDDDDDDDDDDD
Z
Note 6: The turn-around time (TA) is used to avoid bus contention during a read cycle. For a read, the external PHY
drives the second bit of the turn-around time to 0 and then drives the MSB of the read data in the following
cycle. For a write, the device drives the first bit of the turn-around time to 1, the second bit of the turn-around
time to 0 and then the MSB of the write data in the following clock cycle.
Note 7: In the IDLE condition, the P0_MDIO output is three-stated and pulled high externally. P0_MDC is driven.
14.3.2 PHY REGISTER HOST ACCESS
The PHY Management Interface (PMI) is used by the Host to access the internal Physical PHYs as well as the external
PHYs on the MII pins (in MAC modes).
14.3.3 EEPROM LOADER PHY REGISTER ACCESS
The PHY Management Interface Access Register (PMI_ACCESS) and PHY Management Interface Data Register
(PMI_DATA) are accessible as part of the Register Data burst sequence of the EEPROM Loader. Refer to Section 12.4,
"EEPROM Loader," on page 353 for additional information.
DS00001925A-page 382
 2015 Microchip Technology Inc.