LAN9353 Datasheet, PDF (139/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
Bits
Description
Type
2
PHY Energy Efficient Ethernet Enable (PHYEEEEN)
When set, enables Energy Efficient Ethernet (EEE) operation in the PHY.
When cleared, EEE operation is disabled.
Refer to Section 9.2.11, "Energy Efficient Ethernet," on page 108 for addi-
tional information.
R/W
NASR
Note 14
1
EDPD Extend Crossover
R/W
When in Energy Detect Power-Down (EDPD) mode (Energy Detect Power-
NASR
Down (EDPWRDOWN) = 1), setting this bit to 1 extends the crossover time _{Note 14}
by 2976 ms.
Default
Note 15
0b
0 = Crossover time extension disabled
1 = Crossover time extension enabled (2976 ms)
0
Extend Manual 10/100 Auto-MDIX Crossover Time
R/W
1b
When Auto-Negotiation is disabled, setting this bit extends the Auto-MDIX
NASR
crossover time by 32 sample times (32 * 62 ms = 1984 ms). This allows the _{Note 14}
link to be established with a partner PHY that has Auto-Negotiation enabled.
When Auto-Negotiation is enabled, this bit has no affect.
It is recommended that this bit is set when disabling AN with Auto-MDIX
enabled.
Note 14: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Reg-
ister (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the
PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set.
Note 15: The default value of this bit is a 0 if in 100BASE-FX mode, otherwise the default value of this bit is deter-
mined by the Energy Efficient Ethernet Enable Strap (EEE_enable_strap_1 for PHY A, EEE_en-
able_strap_2 for PHY B). Refer to Section 7.0, "Configuration Straps," on page 67 for more information.
 2015 Microchip Technology Inc.
DS00001925A-page 139