LAN9353 Datasheet, PDF (303/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.7.3.14 Switch Engine DIFFSERV Table Write Data Register (SWE_DIFFSERV_TBL_WR_DATA)
Register #:
1812h
Size:
32 bits
This register is used to write the DIFFSERV table. The DIFFSERV table is not initialized upon reset on power-up. If
DIFFSERV is enabled, the full table should be initialized by the host.
Bits
Description
31:3 RESERVED
2:0 DIFFSERV Priority
These bits specify the assigned receive priority for IP packets with a ToS/CS
field that matches this index.
Type
RO
R/W
Default
-
000b
10.7.3.15 Switch Engine DIFFSERV Table Read Data Register (SWE_DIFFSERV_TBL_RD_DATA)
Register #:
1813h
This register is used to read the DIFFSERV table.
Size:
32 bits
Bits
Description
31:3 RESERVED
2:0 DIFFSERV Priority
These bits specify the assigned receive priority for IP packets with a ToS/CS
field that matches this index.
10.7.3.16 Switch Engine DIFFSERV Table Command Status Register
(SWE_DIFFSERV_TBL_CMD_STS)
Type
RO
RO
Register #:
1814h
Size:
This register indicates the current DIFFSERV command status.
32 bits
Default
-
000b
Bits
Description
31:1 RESERVED
0
Operation Pending
When set, this bit indicates that the read or write command is taking place.
This bit self-clears once the command has finished.
Type
RO
RO
SC
Default
-
0b
 2015 Microchip Technology Inc.
DS00001925A-page 303