LAN9353 Datasheet, PDF (320/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.7.3.38 Switch Engine Port 1 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_1)
Register #:
1859h
Size:
32 bits
This register counts the number of MAC addresses on Port 1 that were not learned or were overwritten by a different
address due to address table space limitations.
Bits
Description
31:0 Learn Discard
This field is a count of MAC addresses not learned or overwritten and is
cleared when read.
Note: This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100 Mbps is approximately 481 hours.
Type
RC
Default
00000000h
10.7.3.39 Switch Engine Port 2 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_2)
Register #:
185Ah
Size:
32 bits
This register counts the number of MAC addresses on Port 2 that were not learned or were overwritten by a different
address due to address table space limitations.
Bits
Description
31:0 Learn Discard
This field is a count of MAC addresses not learned or overwritten and is
cleared when read.
Note: This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100 Mbps is approximately 481 hours.
10.7.3.40 Switch Engine Interrupt Mask Register (SWE_IMR)
Type
RC
Default
00000000h
Register #:
1880h
Size:
32 bits
This register contains the Switch Engine interrupt mask, which masks the interrupts in the Switch Engine Interrupt Pend-
ing Register (SWE_IPR). All Switch Engine interrupts are masked by setting the Interrupt Mask bit. Clearing this bit will
unmask the interrupts. Refer to Section 8.0, "System Interrupts," on page 84 for more information.
Bits
Description
31:1 RESERVED
0
Interrupt Mask
When set, this bit masks interrupts from the Switch Engine. The status bits in
the Switch Engine Interrupt Pending Register (SWE_IPR) are not affected.
Type
RO
R/W
Default
-
1b
DS00001925A-page 320
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