LAN9353 Datasheet, PDF (361/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
13.0 MII DATA INTERFACES
This chapter describes the interconnect paths between the various modules including the 3-port Switch Fabric, the
device pins and the Physical PHYs. MII/RMII timing is also detailed in Section 13.4, "Switch Fabric Timing Require-
ments".
13.1 Port 0 Data Path
The MII Data Interface is used to connect the Switch Fabric port to the external pins, to select between PHY and MAC
modes and to emulate an RMII/MII PHY or MAC.
13.1.1 PORT 0 MII MAC MODE
When operating in MII MAC mode, the Switch Fabric MAC output signals are routed to the device’s MII output pins
(P0_OUTD[3:0], P0_OUTER and P0_OUTDV). The Switch Fabric MAC inputs are sourced from the MII input pins
(P0_IND[3:0], P0_INDV, P0_INER, P0_COL, P0_CRS, P0_OUTCLK and P0_INCLK). MII MAC mode can operate at
up to 200 Mbps with the speed determined by the PHY’s clock rate.
13.1.2 PORT 0 RMII MAC MODE
When operating in RMII MAC mode, the MII Data Interface mimics the operation of an RMII MAC and is used when
interfacing to an external PHY that does not support the full MII interface. The RMII interface uses a subset of the MII
pins. The P0_OUTD[1:0], P0_OUTDV, P0_IND[1:0], P0_INDV and P0_REFCLK pins are the only MII pins used to com-
municate with the external PHY in this mode. RMII MAC mode operates at 10 or 100 Mbps.
13.1.2.1 Reference Clock Selection
The 50 MHz RMII reference clock can be selected from either the P0_REFCLK pin input or the internal 50 MHz clock.
The choice is based on the setting of the RMII Clock Direction bit of the Port x Virtual PHY Special Control/Status Reg-
ister (VPHY_SPECIAL_CONTROL_STATUS_x). A low selects P0_REFCLK and a high selects the internal 50 MHz
clock. The high setting also enables P0_REFCLK as an output to be used as the reference clock to the PHY.
13.1.2.2 Clock Drive Strength
When P0_REFCLK is configured as an output via the RMII Clock Direction bit of the Port x Virtual PHY Special Control/
Status Register (VPHY_SPECIAL_CONTROL_STATUS_x), its drive strength is based on the setting of the RMII/Turbo
MII Clock Strength bit of the Port x Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STA-
TUS_x). A low selects 12 mA, a high selects 16 mA.
13.1.3 PORT 0 MII PHY MODE
When operating in MII PHY mode, the MII Data Interface mimics the operation of an MII PHY by supplying the RX and
TX clocks, creating the CRS and COL signals and optionally looping back the MII transmissions. It also provides the
collision test function for the external MII pins or Switch Fabric and can loop back the Switch Fabric’s transmissions. MII
PHY mode can operate at up to 200 Mbps (Turbo mode).
The MII pins P0_INCLK, P0_OUTCLK, P0_COL and P0_CRS, which are inputs when in MII MAC mode, are outputs
when in MII PHY mode.
13.1.3.1 Isolate
When in MII PHY mode, if the Isolate (VPHY_ISO) bit of the Port x Virtual PHY Basic Control Register (VPHY_BA-
SIC_CTRL_x) is set, MII data path output pins are three-stated, the pull-ups and pull-downs are disabled and the MII
data path input pins are ignored (disabled into the non-active state and powered down). Setting the Isolate (VPHY_ISO)
bit does not cause isolation of the MII management pins and does not affect MII MAC mode.
13.1.3.2 Turbo Operation
Turbo (200 Mbps) operation is facilitated in MII PHY mode via the Turbo Mode Enable bit of the Port x Virtual PHY Spe-
cial Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS_x). When set, this bit changes the data rate of the
MII PHY from 100 Mbps to 200 Mbps. The Speed Select LSB (VPHY_SPEED_SEL_LSB) bit of the Port x Virtual PHY
Basic Control Register (VPHY_BASIC_CTRL_x) toggles between 10 and 200 Mbps operation when Turbo Mode
Enable is set.
 2015 Microchip Technology Inc.
DS00001925A-page 361