LAN9353 Datasheet, PDF (241/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.6.6 SWITCH FABRIC MAC ADDRESS HIGH REGISTER (SWITCH_MAC_ADDRH)
Offset:
1F0h
Size:
32 bits
This register contains the upper 16 bits of the MAC address used by the switch for Pause frames. This register is used
in conjunction with Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL). The contents of this register
are optionally loaded from the EEPROM at power-on through the EEPROM Loader if a programmed EEPROM is
detected. The least significant byte of this register (bits [7:0]) is loaded from address 05h of the EEPROM. The second
byte (bits [15:8]) is loaded from address 06h of the EEPROM. The Host can update the contents of this field after the
initialization process has completed.
Refer to Section 10.6.7, "Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL)" for information on how
this address is loaded by the EEPROM Loader. Section 12.4, "EEPROM Loader," on page 353 contains additional
details on using the EEPROM Loader.
Bits
Description
31:23 RESERVED
22 DiffPauseAddr
When set, each port may have a unique MAC address.
21:20
Port 2 Physical Address [41:40]
When DiffPauseAddr is set, these bits are used as bits 41 and 40 of the MAC
Address for Port 2.
19:18
Port 1 Physical Address [41:40]
When DiffPauseAddr is set, these bits are used as bits 41 and 40 of the MAC
Address for Port 1.
17:16
Port 0 Physical Address [41:40]
When DiffPauseAddr is set, these bits are used as bits 41 and 40 of the MAC
Address for Port 0.
15:0 Physical Address[47:32]
This field contains the upper 16-bits (47:32) of the physical address of the
Switch Fabric MACs. Bits 41 and 10 are ignored if DiffPauseAddr is set.
Type
RO
R/W
R/W
R/W
R/W
R/W
Default
-
0b
10b
01b
00b
FFFFh
 2015 Microchip Technology Inc.
DS00001925A-page 241