LAN9353 Datasheet, PDF (228/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
- Case 11 - Asymmetric pause from partner (towards switch port)
10.5.2 EEE ENABLE LOGIC
Each Switch Fabric port (0,1,2) is provided with an input which permits the generation and decoding of EEE LPI signal-
ing. These signals are in addition to the Switch Fabric ports’ Energy Efficient Ethernet (EEE_ENABLE) bits and are used
to check various port conditions such as speed, duplex and mode.
Normally, in order to permit EEE functions, the port must be in internal PHY mode or MII MAC mode, the port speed
must be 100 Mbps, the current duplex must be full and the auto-negotiation result must indicate that both the local and
partner device support EEE 100 Mbps. In order to prevent an unstable link condition, the PHY link status also must indi-
cate “up” for one second.
10.5.2.1 Port 0
Port 0 may only perform EEE functions when in MII MAC mode. The port speed, link status and auto-negotiation result
are not available in MII MAC mode and are not considered. The port duplex comes from the Port 0 Virtual PHY, Section
9.3.2, "Virtual PHY in MAC Modes," on page 182.
Port 0 does not perform EEE functions when in MII PHY mode or in RMII MAC or PHY modes.
10.5.2.2 Port 1
Port 1 only performs EEE functions when in internal PHY mode. The port speed, duplex, link status and auto-negotiation
result come from physical PHY A.
Port 1 does not perform EEE functions when in RMII MAC or PHY modes.
10.5.2.3 Port 2
The port speed, duplex, link status and auto-negotiation result come from physical PHY B.
10.5.3 SWITCH FABRIC CSR INTERFACE
The Switch Fabric CSRs provide register level access to the various parameters of the Switch Fabric. Switch Fabric
related registers can be classified into two main categories based upon their method of access: direct and indirect.
The directly accessible Switch Fabric registers are part of the main system CSRs and are detailed in Section 10.6,
"Switch Fabric Interface Logic Registers," on page 231. These registers provide Switch Fabric manual flow control
(Ports 0-2), data/command registers (for access to the indirect Switch Fabric registers) and switch MAC address con-
figuration.
The indirectly accessible Switch Fabric registers reside within the Switch Fabric and must be accessed indirectly via the
Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA) and the Switch Fabric CSR Interface Command
Register (SWITCH_CSR_CMD) or the set of Switch Fabric CSR Interface Direct Data Registers (SWITCH_CSR_DI-
RECT_DATA). The indirectly accessible Switch Fabric CSRs provide full access to the many configurable parameters
of the Switch Engine, Buffer Manager and each switch port. The Switch Fabric CSRs are detailed in Section 10.7,
"Switch Fabric Control and Status Registers," on page 246.
10.5.4 SWITCH FABRIC CSR WRITES
To perform a write to an individual Switch Fabric register, the desired data must first be written into the Switch Fabric
CSR Interface Data Register (SWITCH_CSR_DATA). The write cycle is initiated by performing a single write to the
Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) with the CSR Busy (CSR_BUSY) bit set, the
CSR Address (CSR_ADDR[15:0]) field set to the desired register address, the Read/Write (R_nW) bit cleared, the Auto
Increment (AUTO_INC) and Auto Decrement (AUTO_DEC) fields cleared and the desired CSR Byte Enable
(CSR_BE[3:0]) bits selected. The completion of the write cycle is indicated by the clearing of the CSR Busy
(CSR_BUSY) bit.
A second write method may be used which utilizes the auto increment/decrement function of the Switch Fabric CSR
Interface Command Register (SWITCH_CSR_CMD) for writing sequential register addresses. When using this method,
the Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) must first be written with the Auto Incre-
ment (AUTO_INC) or Auto Decrement (AUTO_DEC) bit set, the CSR Address (CSR_ADDR[15:0]) field written with the
desired register address, the Read/Write (R_nW) bit cleared and the desired CSR byte enable bits selected (typically
all set). The write cycles are then initiated by writing the desired data into the Switch Fabric CSR Interface Data Register
(SWITCH_CSR_DATA). The completion of the write cycle is indicated by the clearing of the CSR Busy (CSR_BUSY)
DS00001925A-page 228
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