LAN9353 Datasheet, PDF (226/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.4.7 COUNTERS
A counter is maintained per port that contains the number of packets dropped due to buffer space limits and ingress rate
limit discarding (Red and random Yellow dropping). These counters are accessible via the following registers:
• Buffer Manager Port 0 Drop Count Register (BM_DRP_CNT_SRC_0)
• Buffer Manager Port 1 Drop Count Register (BM_DRP_CNT_SRC_1)
• Buffer Manager Port 2 Drop Count Register (BM_DRP_CNT_SRC_2)
A counter is maintained per port that contains the number of packets dropped due solely to ingress rate limit discarding
(Red and random Yellow dropping). This count value can be subtracted from the drop counter, as described above, to
obtain the drop counts due solely to buffer space limits. The ingress rate drop counters are accessible via the following
registers:
• Buffer Manager Port 0 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_0)
• Buffer Manager Port 1 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_1)
• Buffer Manager Port 2 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_2)
10.5 Switch Fabric Interface Logic
10.5.1 FLOW CONTROL ENABLE LOGIC
Each Switch Fabric port (0,1,2) is provided with two flow control enable inputs, one for transmission and one for recep-
tion. Flow control on transmission allows the transmitter to generate back pressure in half-duplex mode and pause pack-
ets in full-duplex. Flow control in reception enables the reception of pause packets to pause transmissions.
The state of these enables is based on the state of the port’s duplex and Auto-Negotiation settings and results, provided
by the attached PHY. For port 0, the PHY is Virtual PHY 0. For port 1, the PHY is either Physical PHY A or Virtual PHY
1, with the appropriate PHY’s signals chosen based on the operation mode of the port (internal PHY vs. external pins).
For port 2, the PHY is Physical PHY B. The PHYs’ advertised pause flow control abilities are set via the Symmetric
Pause and Asymmetric Pause bits of the PHYs’ Auto-Negotiation Advertisement Register. This allows the PHY to adver-
tise its flow control abilities and auto-negotiate the flow control settings with its link partner. The link partners’ advertised
pause flow control abilities are returned via the Symmetric Pause and Asymmetric Pause bits of the PHYs’ Auto-Nego-
tiation Link Partner Base Ability Register.
The pause flow control settings may also be manually set via the manual flow control registers (Port 1 Manual Flow
Control Register (MANUAL_FC_1), Port 2 Manual Flow Control Register (MANUAL_FC_2) or Port 0 Manual Flow Con-
trol Register (MANUAL_FC_0)). Table 10-5 details the Switch Fabric flow control enable logic. These registers allow the
Switch Fabric ports flow control settings to be manually set when Auto-Negotiation is disabled or the respective manual
flow control select bit is set. The currently enabled duplex and flow control settings can also be monitored via these reg-
isters.
When in half-duplex mode, the transmit flow control (back pressure) enable is determined directly by the BP_EN_x bit
of the port’s manual flow control register. When Auto-Negotiation is disabled or the MANUAL_FC_x bit of the port’s man-
ual flow control register is set, the switch port flow control enables during full-duplex are determined by the TX_FC_x
and RX_FC_x bits of the port’s manual flow control register. When Auto-Negotiation is enabled and the MANUAL_FC_x
bit is cleared, the switch port flow control enables during full-duplex are determined by Auto-Negotiation.
Note: The flow control values in the PHYs’ Auto-Negotiation Advertisement Register are not affected by the values
of the manual flow control register.
DS00001925A-page 226
 2015 Microchip Technology Inc.