LAN9353 Datasheet, PDF (379/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 14-1: SMI FRAME FORMAT
Preamble Start
READ
32 1’s
01
WRITE 32 1’s
01
Op
Cod
e
10
01
PHY
Address
Note 1
1AAAA
_9876
1AAAA
_9876
Register
Address
Note 1
AAAAA
54321
AAAAA
54321
Turn-
Around
Time
Note 2
Z0
10
Data
DDDDDDDDDDDDDDDD
1111110000000000
5432109876543210
DDDDDDDDDDDDDDDD
1111110000000000
5432109876543210
Idle
Note 3
Z
Z
Note 1: PHY Address bit 4 is 1 for SMI commands. PHY Address 3:0 form system register address bits 9:6. The
Register Address field forms the system register address bits 5:1.
Note 2: The turn-around time (TA) is used to avoid contention during a read cycle. For a read, the device drives the
second bit of the turn-around time to 0 and then drives the MSB of the read data in the following clock cycle.
For a write, the external host drives the first bit of the turn-around time to 1, the second bit of the turn-around
time to 0 and then the MSB of the write data in the following clock cycle.
Note 3: In the IDLE condition, the MDIO output is three-stated and pulled high externally.
14.2.3.1 Read Sequence
In a read sequence, the host sends the 32-bit preamble, 2-bit start of frame, 2-bit op-code, 5-bit PHY Address and the
5-bit Register Address. The next clock is the first bit of the turn-around time in which the device continues to three-state
MDIO. On the next rising edge of MDC, the device drives MDIO low. For the next 16 rising edges, the device drives
the output data. On the final clock, the device once again three-states MDIO.
The host processor is required to perform two consecutive 16-bit reads to complete a single DWORD transfer. No order-
ing requirements exist. The processor can access either the low or high WORD first, as long as the next read is per-
formed from the other WORD. If a read to the same WORD is performed, the combined data read pair is invalid and
should be re-read. This is not a fatal error. The device will simply reset the read counters and restart a new cycle on the
next read.
Note: Selected registers are readable as 16-bit registers, as noted in their register descriptions. For these regis-
ters, only one 16-bit read may be performed without the need to read the other word.
Note: SMI reads from unused register addresses return all zeros. This differs from unused PHY registers which
leave MDIO un-driven.
SPECIAL CSR HANDLING
Live Bits
Since data is read serially, in order to prevent the host from reading a potentially changing value (such as a live bit or a
counter that spans across two WORDs), 32-bits of register data are latched (registered) at the beginning of the first
WORD of a DWORD transfer and held until the end of the second WORD of the DWORD.
Change on Read Registers and FIFOs
Any register that is affected by a read operation (e.g. a clear on read bit or FIFO) is updated once the output shift of the
second WORD has started. In the event that all bits are not read, the register is still affected and any prior data is lost.
It is assumed that the second read is from the same register and opposite WORD. There is no hardware check.
Change on Read Live Register Bits
As described above, the current value from a register with live bits (as is the case of any register) is saved before the
data is shifted out. Although a hardware event that occurs following the data capture would still update the live bit(s),
the live bit(s) will be affected (cleared, etc.) once the output shift has started and the hardware event would be lost. In
order to prevent this, the individual CSRs defer the hardware event update until after the read indication.
 2015 Microchip Technology Inc.
DS00001925A-page 379