LAN9353 Datasheet, PDF (385/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
14.3.5.2 PHY Management Interface Access Register (PMI_ACCESS)
Offset:
0A8h
Size:
32 bits
This register is used to control the management cycles to the PHYs. A PHY access is initiated when this register is writ-
ten. This register is used in conjunction with the PHY Management Interface Data Register (PMI_DATA) to perform read
and write operations to the PHYs.
Bits
Description
31:16
15:11
10:6
RESERVED
PHY Address (PHY_ADDR)
These bits select the PHY device being accessed. Refer to Section 9.1.1,
"PHY Addressing," on page 94 for information on PHY address assignments.
Note: The EEPROM Loader can only perform register write operations.
MII Register Index (MIIRINDA)
These bits select the desired MII register in the PHY. Refer to Section 9.2.20,
"Physical PHY Registers," on page 120 for detailed descriptions on all PHY
registers.
Note: The EEPROM Loader can only perform register write operations.
5:2 RESERVED
1
MII Write (MIIWnR)
Setting this bit informs the PHY that the access will be a write operation using
the PHY Management Interface Data Register (PMI_DATA). If this bit is
cleared, the access will be a read operation, returning data into the PHY
Management Interface Data Register (PMI_DATA).
Note: The EEPROM Loader can only perform register write operations.
Note: The EEPROM Loader typically only performs PMI write operations
since it can not read registers.
0
MII Busy (MIIBZY)
This bit must be read as 0 before writing to the PHY Management Interface
Data Register (PMI_DATA) or PHY Management Interface Access Register
(PMI_ACCESS) registers. This bit is automatically set when this register is
written. During a PHY register access, this bit will be set, signifying a read or
write access is in progress. This is a self-clearing (SC) bit that will return to 0
when the PHY register access has completed.
During a PHY register write, the PHY Management Interface Data Register
(PMI_DATA) must be kept valid until this bit has cleared.
During a PHY register read, the PHY Management Interface Data Register
(PMI_DATA) register is valid after this bit has cleared.
Type
RO
R/W
R/W
RO
R/W
RO
SC
Note: The EEPROM Loader contains logic which directly checks this bit.
Default
-
00000b
00000b
-
0b
0b
 2015 Microchip Technology Inc.
DS00001925A-page 385