LAN9353 Datasheet, PDF (203/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.0 SWITCH FABRIC
10.1 Functional Overview
The Switch Fabric contains a 3-port VLAN layer 2 Switch Engine that supports untagged, VLAN tagged and priority
tagged frames. The Switch Fabric provides an extensive feature set which includes spanning tree protocol support, mul-
ticast packet filtering and Quality of Service (QoS) packet prioritization by VLAN tag, destination address, port default
value or DIFFSERV/TOS, allowing for a range of prioritization implementations. 32k of buffer RAM allows for the storage
of multiple packets while forwarding operations are completed and a 512 entry forwarding table provides room for MAC
address forwarding tables. Each port is allocated a cluster of 4 dynamic QoS queues which allow each queue size to
grow and shrink with traffic, effectively utilizing all available memory. This memory is managed dynamically via the Buffer
Manager block within the Switch Fabric. All aspects of the Switch Fabric are managed via the Switch Fabric configura-
tion and status registers (CSR), which are indirectly accessible via the system control and status registers.
The Switch Fabric consists of these major blocks:
• Switch Fabric Control and Status Registers - These registers provide access to various Switch Fabric parameters
for configuration and monitoring.
• 10/100 Ethernet MAC - A total of three MACs are included in the Switch Fabric which provide basic 10/100 Ether-
net functionality for each Switch Fabric port.
• Switch Engine (SWE) - This block is the core of the Switch Fabric and provides VLAN layer 2 switching for all
three switch ports.
• Buffer Manager (BM) - This block provides control of the free buffer space, transmit queues and scheduling.
• Switch Fabric Interface Logic - This block provides some auxiliary registers and interfaces the Switch Fabric Con-
trol and Status Registers to the rest of the device. It also enables the flow control functions based on various set-
tings and port conditions.
Refer to FIGURE 2-1: Internal Block Diagram on page 9 for details on the interconnection of the Switch Fabric blocks
within the device.
10.2 10/100 Ethernet MAC
The Switch Fabric contains three 10/100 MAC blocks, one for each switch port (0,1,2). The 10/100 MAC provides the
basic 10/100 Ethernet functionality, including transmission deferral and collision back-off/retry, receive/transmit FCS
checking and generation, receive/transmit pause flow control and transmit back pressure. The 10/100 MAC also
includes RX and TX FIFOs and per port statistic counters.
10.2.1 RECEIVE MAC
The receive MAC (IEEE 802.3) sublayer decomposes Ethernet packets acquired via the internal MII interface by strip-
ping off the preamble sequence and Start of Frame Delimiter (SFD). The receive MAC checks the FCS, the MAC Control
Type and the byte count against the drop conditions. The packet is stored in the RX FIFO as it is received.
The receive MAC determines the validity of each received packet by checking the Type field, FCS and oversize or
undersize conditions. All bad packets will be either immediately dropped or marked (at the end) as bad packets.
Oversized packets are normally truncated at 1519 or 1523 (VLAN tagged) octets and marked as erroneous. The MAC
can be configured to accept packets up to 2048 octets (inclusive), in which case the oversize packets are truncated at
2048 bytes and marked as erroneous.
Undersized packets are defined as packets with a length less than the minimum packet size. The minimum packet size
is defined to be 64 bytes, exclusive of preamble sequence and SFD, regardless of the occurrence of a VLAN tag.
The FCS and length/type fields of the frame are checked to detect if the packet has a valid MAC control frame. When
the MAC receives a MAC control frame with a valid FCS and determines the operation code is a pause command (Flow
Control frame), the MAC will load its internal pause counter with the Number_of_Slots variable from the MAC control
frame just received. Anytime the internal pause counter is zero, the transmit MAC will be allowed to transmit (XON). If
the internal pause counter is not zero, the receive MAC will not allow the transmit MAC to transmit (XOFF). When the
transmit MAC detects an XOFF condition it will continue to transmit the current packet, terminating transmission after
the current packet has been transmitted until receiving the XON condition from the receive MAC. The pause counter will
begin to decrement at the end of the current transmission or immediately if no transmission is underway. If another
pause command is received while the transmitter is already in pause, the new pause time indicated by the Flow Control
 2015 Microchip Technology Inc.
DS00001925A-page 203