LAN9353 Datasheet, PDF (164/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
9.2.20.31 PHY x Wakeup Filter Configuration Register B (PHY_WUF_CFGB_x)
Index (In Decimal): 3.32786
Size:
16 bits
Bits
Description
Type
15:0 Filter CRC-16
R/W/
This field specifies the expected 16-bit CRC value for the filter that should be _NASR
obtained by using the pattern offset and the byte mask programmed for the fil- _{Note 28}
ter. This value is compared against the CRC calculated on the incoming
frame, and a match indicates the reception of a Wakeup Frame.
Default
0000h
Note 28: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Reg-
ister (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the
PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set.
DS00001925A-page 164
 2015 Microchip Technology Inc.