LAN9353 Datasheet, PDF (8/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
2.0 GENERAL DESCRIPTION
The LAN9353 is a full featured, 3 port 10/100 managed Ethernet switch designed for embedded applications where per-
formance, flexibility, ease of integration and system cost control are required. The LAN9353 combines all the functions
of a 10/100 switch system, including the Switch Fabric, packet buffers, Buffer Manager, Media Access Controllers
(MACs), PHY transceivers, and serial management. IEEE 1588v2 is supported via the integrated IEEE 1588v2 hard-
ware time stamp unit, which supports end-to-end and peer-to-peer transparent clocks. The LAN9353 complies with the
IEEE 802.3 (full/half-duplex 10BASE-T and 100BASE-TX) Ethernet protocol, IEEE 802.3az Energy Efficient Ethernet
(EEE) (100Mbps only), and 802.1D/802.1Q network management protocol specifications, enabling compatibility with
industry standard Ethernet and Fast Ethernet applications. 100BASE-FX is supported via an external fiber transceiver.
At the core of the device is the high performance, high efficiency 3 port Ethernet Switch Fabric. The Switch Fabric con-
tains a 3 port VLAN layer 2 Switch Engine that supports untagged, VLAN tagged, and priority tagged frames. The Switch
Fabric provides an extensive feature set which includes spanning tree protocol support, multicast packet filtering and
Quality of Service (QoS) packet prioritization by VLAN tag, destination address, port default value or DIFFSERV/TOS,
allowing for a range of prioritization implementations. 32K of buffer RAM allows for the storage of multiple packets while
forwarding operations are completed, and a 512 entry forwarding table provides ample room for MAC address forward-
ing tables. Each port is allocated a cluster of 4 dynamic QoS queues which allow each queue size to grow and shrink
with traffic, effectively utilizing all available memory. This memory is managed dynamically via the Buffer Manager block
within the Switch Fabric. All aspects of the Switch Fabric are managed via the Switch Fabric configuration and status
registers, which are indirectly accessible via the system control and status registers.
The LAN9353 provides 3 switched ports. Each port is fully compliant with the IEEE 802.3 standard and all internal MACs
and PHYs support full/half duplex 10BASE-T and 100BASE-TX operation. The LAN9353 provides 2 on-chip PHYs, 2
Virtual PHYs and 3 MACs. The Virtual PHY and the third MAC are used to connect the Switch Fabric to an external MAC
or PHY. In MAC mode, the device can be connected to an external PHY via the MII/RMII/Turbo MII interface. In PHY
mode, the device can be connected to an external MAC via the MII/RMII/Turbo MII interface. Optionally, the internal
PHY on Port 1 can be disabled and the associated Switch Fabric port operated in the RMII PHY or RMII MAC modes.
All ports support automatic or manual full duplex flow control or half duplex backpressure (forced collision) flow control.
2K jumbo packet (2048 byte) support allows for oversized packet transfers, effectively increasing throughput while
decreasing CPU load. All MAC and PHY related settings are fully configurable via their respective registers within the
device.
The integrated I²C and SMI slave controllers allow for full serial management of the device via the integrated I²C or MII
interface, respectively. The inclusion of these interfaces allows for greater flexibility in the incorporation of the device
into various designs. It is this flexibility which allows the device to operate in 2 different modes and under various man-
agement conditions. In both MAC and PHY modes, the device can be SMI managed or I²C managed. This flexibility in
management makes the LAN9353 a candidate for virtually all switch applications.
The LAN9353 supports numerous power management and wakeup features. The LAN9353 can be placed in a reduced
power mode and can be programmed to issue an external wake signal (IRQ) via several methods, including “Magic
Packet”, “Wake on LAN”, wake on broadcast, wake on perfect DA, and “Link Status Change”. This signal is ideal for
triggering system power-up using remote Ethernet wakeup events. The device can be removed from the low power state
via a host processor command or one of the wake events.
The LAN9353 contains an I²C master EEPROM controller for connection to an optional EEPROM. This allows for the
storage and retrieval of static data. The internal EEPROM Loader can be optionally configured to automatically load
stored configuration settings from the EEPROM into the device at reset. The I²C management slave and master
EEPROM controller share common pins.
In addition to the primary functionality described above, the LAN9353 provides additional features designed for
extended functionality. These include a configurable 16-bit General Purpose Timer (GPT), a 32-bit 25MHz free running
counter, a configurable GPIO/LED interface, and IEEE 1588 time stamping on all ports and all GPIOs. The IEEE time
stamp unit provides a 64-bit tunable clock for accurate PTP timing and a timer comparator to allow time based interrupt
generation.
The LAN9353 can be configured to operate via a single 3.3V supply utilizing an integrated 3.3V to 1.2V linear regulator.
The linear regulator may be optionally disabled, allowing usage of a high efficiency external regulator for lower system
power dissipation.
The LAN9353 is available in commercial and industrial temperature ranges. Figure 2-1 provides an internal block dia-
gram of the LAN9353.
DS00001925A-page 8
 2015 Microchip Technology Inc.