LAN9353 Datasheet, PDF (56/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
6.2.3
6.2.3.1
RESET REGISTERS
Reset Control Register (RESET_CTL)
Offset:
1F8h
Size:
32 bits
This register contains software controlled resets.
Note:
This register can be read while the device is in the reset or not ready / power savings states without leaving
the host interface in an intermediate state. If the host interface is in a reset state, returned data may be
invalid.
It is not necessary to read all four bytes of this register. DWORD access rules do not apply to this register.
Bits
Description
31:7 RESERVED
6
RESERVED
5
RESERVED
4
Virtual PHY 1 Reset (VPHY_1_RST)
Setting this bit resets Virtual PHY 1. When the Virtual PHY is released from
reset, this bit is automatically cleared. All writes to this bit are ignored while
this bit is set.
Note: This bit is not accessible via the EEPROM Loader’s register
initialization function (Section 12.4.5).
3
Virtual PHY 0 Reset (VPHY_0_RST)
Setting this bit resets Virtual PHY 0. When the Virtual PHY is released from
reset, this bit is automatically cleared. All writes to this bit are ignored while
this bit is set.
Note: This bit is not accessible via the EEPROM Loader’s register
initialization function (Section 12.4.5).
Type
RO
RO
RO
R/W
SC
R/W
SC
Default
-
-
-
0b
0b
DS00001925A-page 56
 2015 Microchip Technology Inc.