LAN9353 Datasheet, PDF (65/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
Bits
Description
8:7 RESERVED
6:5 RESERVED
4
RESERVED
3:1 RESERVED
0
Device Ready (READY)
When set, this bit indicates that the device is ready to be accessed. Upon
power-up, RST# reset, return from power savings states, or digital reset, the
host processor may interrogate this field as an indication that the device has
stabilized and is fully active.
This rising edge of this bit will assert the Device Ready (READY) bit in
INT_STS and can cause an interrupt if enabled.
Note:
With the exception of the HW_CFG, PMT_CTRL, BYTE_TEST, and
RESET_CTL registers, read access to any internal resources is
forbidden while the READY bit is cleared. Writes to any address
are invalid until this bit is set.
Note: This bit is identical to bit 27 of the Hardware Configuration Register
(HW_CFG).
Type
RO
RO
RO
RO
RO
Default
-
-
-
-
0b
 2015 Microchip Technology Inc.
DS00001925A-page 65