LAN9353 Datasheet, PDF (100/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to the incoming stream. Once
synchronization is achieved, the descrambler locks on this key and is able to descramble incoming data.
Special logic in the descrambler ensures synchronization with the remote transceiver by searching for IDLE symbols
within a window of 4000 bytes (40 us). This window ensures that a maximum packet size of 1514 bytes, allowed by the
IEEE 802.3 standard, can be received with no interference. If no IDLE-symbols are detected within this time-period,
receive operation is aborted and the descrambler re-starts the synchronization process.
The de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /J/K/ Start-of-Stream Delimiter (SSD)
pair at the start of a packet. Once the code-word alignment is determined, it is stored and utilized until the next start of
frame.
9.2.3.5 5B/4B Decoding
The 5-bit code-groups are translated into 4-bit data nibbles according to the 4B/5B table. The translated data is pre-
sented on the internal MII RXD[3:0] signal lines. The SSD, /J/K/, is translated to “0101 0101” as the first 2 nibbles of the
MAC preamble. Reception of the SSD causes the transceiver to assert the receive data valid signal, indicating that valid
data is available on the RXD bus. Successive valid code-groups are translated to data nibbles. Reception of either the
End of Stream Delimiter (ESD) consisting of the /T/R/ symbols, or at least two /I/ symbols causes the transceiver to de-
assert carrier sense and receive data valid signal.
Note: These symbols are not translated into data.
9.2.3.6 Receive Data Valid Signal
The internal MII’s Receive Data Valid signal (RXDV) indicates that recovered and decoded nibbles are being presented
on the RXD[3:0] outputs synchronous to RXCLK. RXDV becomes active after the /J/K/ delimiter has been recognized
and RXD is aligned to nibble boundaries. It remains active until either the /T/R/ delimiter is recognized or link test indi-
cates failure or SIGDET becomes false.
RXDV is asserted when the first nibble of translated /J/K/ is ready for transfer over the Media Independent Interface.
9.2.3.7 Receiver Errors
During a frame, unexpected code-groups are considered receive errors. Expected code groups are the DATA set (0
through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the internal MII’s RXER signal is asserted
and arbitrary data is driven onto the internal MII’s RXD[3:0] lines. Should an error be detected during the time that the /
J/K/ delimiter is being decoded (bad SSD error), RXER is asserted true and the value 1110b is driven onto the RXD[3:0]
lines. Note that the internal MII’s data valid signal (RXDV) is not yet asserted when the bad SSD occurs.
9.2.3.8 100M Receive Data Across the Internal MII Interface
For reception, the 4-bit data nibbles are sent to the MII MAC Interface block. These data nibbles are clocked to the con-
troller at a rate of 25 MHz. RXCLK is the output clock for the internal MII bus. It is recovered from the received data to
clock the RXD bus. If there is no received signal, it is derived from the system reference clock.
9.2.4 10BASE-T TRANSMIT
The 10BASE-T transmitter receives 4-bit nibbles from the internal MII at a rate of 2.5 MHz and converts them to a 10
Mbps serial data stream. The data stream is then Manchester-encoded and sent to the analog transmitter, which drives
a signal onto the twisted pair via the external magnetics.
10BASE-T transmissions use the following blocks:
• MII (digital)
• TX 10M (digital)
• 10M Transmitter (analog)
• 10M PLL (analog)
9.2.4.1 10M Transmit Data Across the Internal MII Interface
For a transmission, the Switch Fabric MAC drives the transmit data onto the internal MII TXD bus and asserts the inter-
nal MII TXEN to indicate valid data. The data is in the form of 4-bit wide 2.5 MHz data.
In half-duplex mode the transceiver loops back the transmitted data, on the receive path. This does not confuse the
MAC/Controller since the COL signal is not asserted during this time. The transceiver also supports the SQE (Heartbeat)
signal.
DS00001925A-page 100
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