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LAN9353 Datasheet, PDF (408/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII
LAN9353
Note: If the original correctionField contains a value of 0x7FFFFFFFFFFFFFFF, it is not modified.
If adjustment to the correctionField would result in a value that is larger than 0x7FFFFFFFFFFFFFFF, that
value is used instead.
• For Delay_Req and Pdelay_Req packets, the value of the Port Delay Asymmetry (DELAY_ASYM[15:0]) field in
the 1588 Port x Asymmetry and Peer Delay Register (1588_ASYM_PEERDLY_x) (for the particular egress port) is
subtracted from the correctionField.
This function is used for one-step end-to-end transparent clocks. If one-step end-to-end transparent clock mode is
not being used, correction field modifications would not be enabled for Delay_Req and PDelay_Req messages.
• The nanoseconds portion of the egress time are added to the correctionField.
• In order to detect and correct for a potential rollover of the nanoseconds portion the clock, egress seconds bits 3:0
minus ingress seconds bits 3:0 (without borrow) is added to the correctionField.
The ingress time is available in bits 3:0 of a reserved byte in the PTP header.
Note: The offset of the reserved byte is specified by the TX PTP 1 Reserved Byte Offset (TX_PTP_1_RSVD_OFF-
SET[5:0]) field in the 1588 Port x TX Modification Register (1588_TX_MOD_x).
Proper operation of the transmitter requires that the reserved byte resides after the versionPTP field and
before the correctionField.
For version 2 of IEEE 1588, the reserved byte at offset 5 should be used.
EGRESS TIME INSERTION - SYNC MESSAGE ALERNATE FUNCTION
While functioning as an ordinary clock master, one-step transmission of Sync messages from the Host S/W requires the
actual egress time to be inserted into the ten byte, originTimestamp field. The 32-bit nanoseconds portion and the lower
32 bits of the seconds portion come from the latency adjusted, 1588 Clock value, saved above at the start of the frame.
The upper 16 bits of seconds are taken from the 1588 TX One-Step Sync Upper Seconds Register (1588_TX_ONE_-
STEP_SYNC_SEC). The Host software is responsible for maintaining this register if required.
Note: Inserting the egress time into the packet is an additional, separately enabled, feature verses the Egress
Time Recording described above.
This function is enabled via the TX PTP Sync Message Egress Time Insertion (TX_PTP_SYNC_TS_INSERT) bit in the
1588 Port x TX Modification Register (1588_TX_MOD_x) and is used only on frames which have bit 7 of the PTP
header’s reserved byte cleared.
Note: The offset of the reserved byte is specified by the TX PTP 1 Reserved Byte Offset (TX_PTP_1_RSVD_OFF-
SET[5:0]) field in the 1588 Port x TX Modification Register (1588_TX_MOD_x).
Proper operation of the transmitter requires that the reserved byte resides after the versionPTP field and
before the correctionField.
For version 2 of IEEE 1588, the reserved byte at offset 5 should be used.
Following the determination of packet format and qualification of the packet as a PTP message above, the PTP header
is checked.
• The versionPTP field of the PTP header is checked against the TX PTP Version (TX_PTP_VERSION[3:0]) field in
the 1588 Port x TX Timestamp Configuration Register (1588_TX_TIMESTAMP_CONFIG_x). Only those mes-
sages with a matching version will have their egress time inserted. A setting of 0 allows any PTP version.
Note: The domainNumber field and alternateMasterFlag in the flagField of the PTP header are not tested.
Note: Support for the IEEE 1588-2002 (v1) packet format is not provided.
EGRESS CORRECTION FIELD TURNAROUND TIME ADJUSTMENT - PDELAY_RESP MESSAGE ALTERNATE
FUNCTION
One-step Pdelay_Resp messages sent by the Host, require their correctionField to be calculated on-the-fly to include
the turnaround time between the ingress of the Pdelay_Req and the egress time of the Pdelay_Resp.
Pdelay_Resp.CF = Pdelay_Req.CF + Pdelay_Resp.egress time - Pdelay_Req.ingress time.
Note: Adjusting the Correction Field in the packet is an additional, separately enabled, feature verses the Egress
Time Recording described above.
DS00001925A-page 408
 2015 Microchip Technology Inc.