LAN9353 Datasheet, PDF (447/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
15.8.23 1588 PORT X RX TIMESTAMP CONFIGURATION REGISTER
(1588_RX_TIMESTAMP_CONFIG_X)
Offset:
Bank:
15Ch
1
Size:
32 bits
This register is used to configure PTP receive message timestamping.
Note:
Port and GPIO registers share a common address space. Port registers are selected by the Bank Select
(BANK_SEL[2:0] in the 1588 Bank Port GPIO Select Register (1588_BANK_PORT_GPIO_SEL). The port
accessed (“x”) is set by the Port Select (PORT_SEL[1:0]) field.
Bits
Description
31:24
23
22
21
RX PTP Domain (RX_PTP_DOMAIN[7:0])
This field specifies the PTP domain in use. If RX PTP Domain Match Enable
(RX_PTP_DOMAIN_EN) is set, the domainNumber in the PTP message
must matches the value in this field in order to recorded the ingress time.
Note:
The host S/W must not change this field while the 1588 Enable
(1588_ENABLE) bit in 1588 Command and Control Register
(1588_CMD_CTL) is set.
RX PTP Domain Match Enable (RX_PTP_DOMAIN_EN)
When this bit is set, the domainNumber in the PTP message is checked
against the value in RX PTP Domain (RX_PTP_DOMAIN[7:0]).
Note:
The host S/W must not change this bit while the 1588 Enable
(1588_ENABLE) bit in 1588 Command and Control Register
(1588_CMD_CTL) is set.
RX PTP Alternate Master Enable (RX_PTP_ALT_MASTER_EN)
When this bit is set, the alternateMasterFlag in the PTP message is checked
for a zero value.
Note:
The host S/W must not change this bit while the 1588 Enable
(1588_ENABLE) bit in 1588 Command and Control Register
(1588_CMD_CTL) is set.
RX PTP UDP Checksum Check Disable (RX_PTP_UDP_CHKSUM_DIS)
When this bit is cleared, ingress times are not saved and ingress messages
are not filtered if the frame has an invalid UDP checksum.
When this bit is set, the UDP checksum check is bypassed and the ingress
time is saved and ingress messages are filtered regardless.
Note:
The host S/W must not change this bit while the 1588 Enable
(1588_ENABLE) bit in 1588 Command and Control Register
(1588_CMD_CTL) is set.
20 RX PTP FCS Check Disable (RX_PTP_FCS_DIS)
When this bit is cleared, ingress times are not saved and ingress messages
are not filtered if the frame has an invalid FCS.
When this bit is set, the FCS check is bypassed.
Note:
The host S/W must not change this bit while the 1588 Enable
(1588_ENABLE) bit in 1588 Command and Control Register
(1588_CMD_CTL) is set.
Type
R/W
R/W
R/W
R/W
R/W
Default
00h
0b
0b
0b
0b
 2015 Microchip Technology Inc.
DS00001925A-page 447