LAN9353 Datasheet, PDF (48/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 5-2: READ AFTER WRITE TIMING RULES (CONTINUED)
After Writing...
General Purpose Timer Con-
figuration Register
(GPT_CFG)
1588 Command and Control
Register (1588_CMD_CTL)
1588 Interrupt Status Register
(1588_INT_STS)
1588 Interrupt Enable Regis-
ter (1588_INT_EN)
Switch Fabric CSR Interface
Data Register (SWITCH_CS-
R_DATA)
General Purpose I/O Interrupt
Status and Enable Register
(GPIO_INT_STS_EN)
wait for this many
nanoseconds...
55
170
70
50
50
60
60
50
60
or Perform this many
Reads of BYTE_TEST…
(assuming T_cyc of 45ns)
before reading...
2
General Purpose Timer Con-
figuration Register
(GPT_CFG)
4
General Purpose Timer Count
Register (GPT_CNT)
2
Interrupt Configuration Regis-
ter (IRQ_CFG)
2
Interrupt Status Register
(INT_STS)
2
1588 Interrupt Status Register
(1588_INT_STS)
2
Interrupt Configuration Regis-
ter (IRQ_CFG)
2
Interrupt Configuration Regis-
ter (IRQ_CFG)
2
Switch Fabric CSR Interface
Command Register
(SWITCH_CSR_CMD)
Note 14
2
Interrupt Configuration Regis-
ter (IRQ_CFG)
Note 14: This timing applies only to the auto-increment and auto-decrement modes of Switch Fabric CSR register
access.
5.2.2 BACK-TO-BACK READ CYCLES
There are also restrictions on specific back-to-back host read operations. These restrictions concern reading specific
registers after reading a resource that has side effects. In many cases there is a delay between reading the device, and
the subsequent indication of the expected change in the control and status register values.
In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have been estab-
lished. These periods are specified in Table 5-3. The host processor is required to wait the specified period of time
between read operations of specific combinations of resources. The wait period is dependent upon the combination of
registers being read.
Performing “dummy” reads of the Byte Order Test Register (BYTE_TEST) register is a convenient way to guarantee that
the minimum wait time restriction is met. Table 5-3 below also shows the number of dummy reads that are required for
back-to-back read operations. The number of BYTE_TEST reads in this table is based on the minimum timing for T_cyc
(45ns). For microprocessors with slower busses the number of reads may be reduced as long as the total time is equal
to, or greater than the time specified in the table. Dummy reads of the BYTE_TEST register are not required as long as
the minimum time period is met.
Note that depending on the host interface mode in use, the basic host interface cycle may naturally provide sufficient
time between reads. It is required of the system design and register access mechanisms to ensure the proper timing.
For example, multiple reads to the same register may occur faster than reads to different registers.
DS00001925A-page 48
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