LAN9353 Datasheet, PDF (457/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
15.8.31 1588 PORT X RX PDELAY_REQ INGRESS TIME NANOSECONDS REGISTER
(1588_RX_PDREQ_NS_X)
Offset:
Bank:
17Ch
1
Size:
32 bits
This register combined with the 1588 Port x RX Pdelay_Req Ingress Time Seconds Register (1588_RX_P-
DREQ_SEC_x) contains the ingress time of the last Pdelay_Req message. This register is automatically updated if the
Auto Update (AUTO) bit is set.
Note:
Port and GPIO registers share a common address space. Port registers are selected by the Bank Select
(BANK_SEL[2:0] in the 1588 Bank Port GPIO Select Register (1588_BANK_PORT_GPIO_SEL). The port
accessed (“x”) is set by the Port Select (PORT_SEL[1:0]) field.
Bits
Description
31 Auto Update (AUTO)
If this bit is set, the TS_NS field in this register, the TS_SEC field in
1588_RX_PDREQ_SEC_x and the CF field in 1588_RX_PDREQ_CF_HI_x /
1588_RX_PDREQ_CF_LO_x are updated when a PDelay_Req message is
received.
When cleared, S/W is responsible to maintain those fields.
Note:
The host S/W must not change this bit while the 1588 Enable
(1588_ENABLE) bit in 1588 Command and Control Register
(1588_CMD_CTL) is set.
30 RESERVED
29:0 Timestamp NanoSeconds (TS_NS)
This field contains the nanoseconds portion of the receive ingress time.
Type
R/W
RO
R/W
Default
0b
-
00000000h
 2015 Microchip Technology Inc.
DS00001925A-page 457