LAN9353 Datasheet, PDF (482/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
16.3.1 GENERAL PURPOSE TIMER CONFIGURATION REGISTER (GPT_CFG)
Offset:
08Ch
Size:
32 bits
This read/write register configures the device’s General Purpose Timer (GPT). The GPT can be configured to generate
host interrupts at the interval defined in this register. The current value of the GPT can be monitored via the General
Purpose Timer Count Register (GPT_CNT). Refer to Section 16.1, "General Purpose Timer," on page 481 for additional
information.
Bits
Description
31:30 RESERVED
29 General Purpose Timer Enable (TIMER_EN)
This bit enables the GPT. When set, the GPT enters the run state. When
cleared, the GPT is halted. On the 1 to 0 transition of this bit, the GPT_LOAD
field of this register will be preset to FFFFh.
28:16
0: GPT Disabled
1: GPT Enabled
RESERVED
15:0 General Purpose Timer Pre-Load (GPT_LOAD)
This value is pre-loaded into the GPT. This is the starting value of the GPT.
The timer will begin decrementing from this value when enabled.
Type
RO
R/W
RO
R/W
Default
-
0b
-
FFFFh
DS00001925A-page 482
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