LAN9353 Datasheet, PDF (513/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
20.6.3 RESET AND CONFIGURATION STRAP TIMING
This diagram illustrates the RST# pin timing requirements and its relation to the configuration strap pins and output
drive. Assertion of RST# is not a requirement. However, if used, it must be asserted for the minimum period specified.
The RST# pin can be asserted at any time, but must not be deasserted until t_purstd after all external power supplies have
reached operational levels. Refer to Section 6.2, "Resets," on page 51 for additional information.
FIGURE 20-4:
RST# PIN CONFIGURATION STRAP LATCHING TIMING
All External
Vopp
Power Supplies
RST#
Configuration
Strap Pins
Output Drive
t_purstd
t_rstia
t_css
t_csh
t_odad

TABLE 20-11: RST# PIN CONFIGURATION STRAP LATCHING TIMING VALUES
Symbol
Description
Min
Typ
Max Units
t_purstd External power supplies at operational level to RST# deasser-
25
ms
tion
t_rstia
t_css
t_csh
t_odad
Note:
RST# input assertion time
Configuration strap pins setup to RST# deassertion
Configuration strap pins hold after RST# deassertion
Output drive after deassertion
The clock input must be stable prior to RST# deassertion.
200
-
200
-
10
-
3
-
-
s
-
ns
-
ns
-
us
Note: Device configuration straps are latched as a result of RST# assertion. Refer to Section 6.2.1, "Chip-Level
Resets," on page 52 for details.
Note: Configuration strap latching and output drive timings shown assume that the Power-On reset has finished
first otherwise the timings in Section 20.6.4, "Power-On and Configuration Strap Timing" apply.
 2015 Microchip Technology Inc.
DS00001925A-page 513