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LAN9353 Datasheet, PDF (330/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII
LAN9353
10.7.4.13 Buffer Manager Egress Port Type Register (BM_EGRSS_PORT_TYPE)
Register #:
1C0Ch
Size:
32 bits
This register is used to configure the egress VLAN tagging rules. See Section 10.4.6, "Adding, Removing and Changing
VLAN Tags," on page 223 for additional details.
Bits
Description
31:23 RESERVED
22 VID/Priority Select Port 2
This bit determines the VID and priority in inserted or changed tags.
0: The default VID of the ingress port / priority calculated on ingress.
1: The default VID / priority of the egress port.
This is only used when the Egress Port Type is set as Hybrid.
21 Insert Tag Port 2
When set, untagged packets will have a tag added. The VID and priority is
determined by the VID/Priority Select Port 2 bit.
The un-tag bit in the VLAN table for the default VLAN ID also needs to be
cleared in order for the tag to be inserted.
This is only used when the Egress Port Type is set as Hybrid.
20 Change VLAN ID Port 2
When set, regular tagged packets will have their VLAN ID overwritten with
the Default VLAN ID of either the ingress or egress port, as determined by
the VID/Priority Select Port 2 bit.
The Change Tag bit also needs to be set.
The un-tag bit in the VLAN table for the incoming VLAN ID also needs to be
cleared, otherwise the tag will be removed instead.
Priority tagged packets will have their VLAN ID overwritten with the Default
VLAN ID of either the ingress or egress port independent of this bit.
This is only used when the Egress Port Type is set as Hybrid.
19 Change Priority Port 2
When set, regular tagged and priority tagged packets will have their Priority
overwritten with the priority determined by the VID/Priority Select Port 2 bit.
For regular tagged packets, the Change Tag bit also needs to be set by soft-
ware.
The un-tag bit in the VLAN table for the incoming VLAN ID also needs to be
cleared, otherwise the tag would be removed instead.
This is only used when the Egress Port Type is set as Hybrid.
Type
RO
R/W
R/W
R/W
R/W
Default
-
0b
0b
0b
0b
DS00001925A-page 330
 2015 Microchip Technology Inc.