LAN9353 Datasheet, PDF (147/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
Bits
Description
4
10Base-T Polarity State (XPOL)
This bit shows the polarity state of the 10Base-T.
Type
RO
Default
0b
0: Normal Polarity
1: Reversed Polarity
3:0 RESERVED
RO
-
Note 23: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Reg-
ister (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the
PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set.
Note 24: The default value of this bit is a 1 if in 100BASE-FX mode, otherwise the default is a 0.
TABLE 9-17: AUTO-MDIX ENABLE AND AUTO-MDIX STATE BIT FUNCTIONALITY
Auto-MDIX Enable
0
0
1
1
Auto-MDIX State
0
1
0
1
Mode
Manual mode, no crossover
Manual mode, crossover
Auto-MDIX mode
RESERVED (do not use this state)
TABLE 9-18: MDIX STRAP FUNCTIONALITY
auto_mdix_strap_x
0
0
1
manual_mdix_strap_x
0
1
x
Mode
Manual mode, no crossover
Manual mode, crossover
Auto-MDIX mode
 2015 Microchip Technology Inc.
DS00001925A-page 147