LAN9353 Datasheet, PDF (87/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
PHY interrupts are enabled/disabled via their respective PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x).
The source of a PHY interrupt can be determined and cleared via the PHY x Interrupt Source Flags Register (PHY_IN-
TERRUPT_SOURCE_x). Unique interrupts are generated based on the following events:
• ENERGYON Activated
• Auto-Negotiation Complete
• Remote Fault Detected
• Link Down (Link Status Negated)
• Link Up (Link Status Asserted)
• Auto-Negotiation LP Acknowledge
• Parallel Detection Fault
• Auto-Negotiation Page Received
• Wake-on-LAN Event Detected
In order for an interrupt event to trigger the external IRQ interrupt pin, the desired PHY interrupt event must be enabled
in the corresponding PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x), the Physical PHY A Interrupt Event
Enable (PHY_INT_A_EN) and/or Physical PHY B Interrupt Event Enable (PHY_INT_B_EN) bits of the Interrupt Enable
Register (INT_EN) must be set and the IRQ output must be enabled via the IRQ Enable (IRQ_EN) bit of the Interrupt
Configuration Register (IRQ_CFG).
For additional details on the Ethernet PHY interrupts, refer to Section 9.2.9, "PHY Interrupts," on page 105.
8.2.4 GPIO INTERRUPTS
Each GPIO of the device is provided with its own interrupt. The top-level GPIO Interrupt Event (GPIO) bit of the Interrupt
Status Register (INT_STS) provides indication that a GPIO interrupt event occurred in the General Purpose I/O Interrupt
Status and Enable Register (GPIO_INT_STS_EN). The General Purpose I/O Interrupt Status and Enable Register (GPI-
O_INT_STS_EN) provides enabling/disabling and status of each GPIO interrupt.
In order for a GPIO interrupt event to trigger the external IRQ interrupt pin, the desired GPIO interrupt must be enabled
in the General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN), the GPIO Interrupt Event
Enable (GPIO_EN) bit of the Interrupt Enable Register (INT_EN) must be set and the IRQ output must be enabled via
the IRQ Enable (IRQ_EN) bit of the Interrupt Configuration Register (IRQ_CFG).
For additional details on the GPIO interrupts, refer to Section 17.2.1, "GPIO Interrupts," on page 485.
8.2.5 POWER MANAGEMENT INTERRUPTS
Multiple Power Management Event interrupt sources are provided by the device. The top-level Power Management
Interrupt Event (PME_INT) bit of the Interrupt Status Register (INT_STS) provides indication that a Power Management
interrupt event occurred in the Power Management Control Register (PMT_CTRL).
The Power Management Control Register (PMT_CTRL) provides enabling/disabling and status of all Power Manage-
ment conditions. These include energy-detect on the PHYs and Wake-On-LAN (Perfect DA, Broadcast, Wake-up frame
or Magic Packet) detection by PHYs A&B.
In order for a Power Management interrupt event to trigger the external IRQ interrupt pin, the desired Power Manage-
ment interrupt event must be enabled in the Power Management Control Register (PMT_CTRL), the Power Manage-
ment Event Interrupt Enable (PME_INT_EN) bit of the Interrupt Enable Register (INT_EN) must be set and the IRQ
output must be enabled via the IRQ Enable (IRQ_EN) bit 8 of the Interrupt Configuration Register (IRQ_CFG).
The power management interrupts are only a portion of the power management features of the device. For additional
details on power management, refer to Section 6.3, "Power Management," on page 58.
8.2.6 GENERAL PURPOSE TIMER INTERRUPT
A GP Timer (GPT_INT) interrupt is provided in the top-level Interrupt Status Register (INT_STS) and Interrupt Enable
Register (INT_EN). This interrupt is issued when the General Purpose Timer Count Register (GPT_CNT) wraps past
zero to FFFFh and is cleared when the GP Timer (GPT_INT) bit of the Interrupt Status Register (INT_STS) is written
with 1.
In order for a General Purpose Timer interrupt event to trigger the external IRQ interrupt pin, the GPT must be enabled
via the General Purpose Timer Enable (TIMER_EN) bit in the General Purpose Timer Configuration Register
(GPT_CFG), the GP Timer Interrupt Enable (GPT_INT_EN) bit of the Interrupt Enable Register (INT_EN) must be set
and the IRQ output must be enabled via the IRQ Enable (IRQ_EN) bit of the Interrupt Configuration Register
(IRQ_CFG).
 2015 Microchip Technology Inc.
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